FXLS8971CF datasheet(48/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

• In motion detection mode with BT_MODE=VDD, use of HPM or FPM mode is not advised. Only the default

LPM mode should be used.

• When BT_MODE=VDD, maximum recommended ODR is 100 Hz. When the data ready interrupt is enabled,

the interrupt line (INT1) will pulse low for TPULSE-MOT seconds (

5 ms typ) for every ODR period. Therefore,

for higher ODRs, the host does not observe DRDY interrupt pulse at every ODR period.

Bit

Name

WAKE_ODR[3:0] / WAKE_DEC[3:0]

SLEEP_ODR[3:0] / SLEEP_DEC[3:0]

Reset (BT_MODE = GND)

Reset (BT_MODE = VDD)

Access

R/W

Table 51. SENS_CONFIG3 register (address 17h) bit allocation

In HPM and LPM modes, a decimation factor is implicit, as specified in Table 52 and Table 53, respectively.

In FPM, the decimation factor for WAKE and SLEEP modes is specified via the same bit-fields (see Table 54 for

the available settings), and along with the WAKE and SLEEP idle time parameter determines the effective ODR.

For example, if

SENS_CONFIG2[WAKE_PM] = 10b, selecting FPM in the WAKE operating mode, the

SENS_CONFIG3 upper nibble is interpreted as the decimation factor for WAKE mode (WAKE_DEC[3:0]) per

Table 54. If a value of 0110b is chosen, for example, a decimation factor of 64 is selected. If WAKE_IDLE[11:0]

is set to 256 (decimal), the effective ODR would be 1 / ((256+1) * (312.5 µs) * 64) = 0.195 Hz.

The effective ODR is determined in a similar manner for the SLEEP operating mode using the SLEEP_DEC[3:0]

and the SLEEP_IDLE[11:0] values.

When operating in HPM or LPM with ODR = 3200 Hz, or in FPM with IDLE_TIME = 0, the first data sample is

produced after a time delay greater than 1 ODR period using Equation 1.

(1)

Note: The IDLE_TIME refers to either WAKE_IDLE[11:0] or SLEEP_IDLE[11:0], depending on current

operating mode.

After this initial delay, all subsequent data samples are made available at the ODR rate. For all other operating

modes and settings the first sample is produced within 1 ODR period.

Notes:

• When the device transitions from WAKE to SLEEP or from SLEEP to WAKE modes there is a 500 µs

(nominal) delay between the last acquisition at the WAKE/SLEEP mode ODR and the first acquisition at the

SLEEP/WAKE mode ODR.

• The ODR may only be changed in Standby mode, with SENS_CONFIG1[ACTIVE] = 0 and

SENS_CONFIG4[INT2_FUNC] = 0.

ODR[3]

ODR[2]

ODR[1]

ODR[0]

ODR Selection

(Hz)

Decimation

selection

(samples)

3200

1600

800

Table 52. WAKE and SLEEP low-power mode ODR and decimation settings

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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