TMP86FS49AIUG datasheet(213/296 Pages) TOSHIBA

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Page 197

TMP86FS49AIUG

16.5 I2C Bus Control

The following registers are used to control the serial bus interface and monitor the operation status of the I2C bus.

Note 1: fc: High-frequency clock [Hz], *: Don't care

Note 2: SBICRA cannot be used with any of read-modify-write instructions such as bit manipulation, etc.

Note 3: Do not set SCK as the frequency that is over 100 kHz.

Note 1: For writing transmitted data, start from the MSB (Bit7).

Note 2: The data which was written into SBIDBR can not be read, since a write data buffer and a read buffer are independent in

SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions such as bit manipulation, etc.

Note 3: *: Don't care

Serial Bus Interface Control Register A

SBICRA

(0F90H)

43210

ACK

SCK

(Initial value: 0000 *000)

Number of transferred bits

ACK = 0

ACK = 1

Write

only

Number of

Clock

Bits

Number of

Clock

Bits

000:

001:

010:

011:

100:

101:

110:

676

111:

ACK

Acknowledgement mode

specification

ACK

Master mode

Slave mode

R/W

Not generate a clock pulse for

an acknowledgement.

Not count a clock pulse for

an acknowledgement.

Generate a clock pulse for an

acknowledgement.

Count a clock pulse for an

acknowledgement.

SCK

Serial clock (fscl) selection

(Output on SCL pin)

[fscl = 1/(2n+1/fc + 8/fc)]

SCK

At fc = 16 MHz

At fc = 8 MHz

At fc = 4 MHz

Write

only

000:

Reserved

100.0 kHz

001:

Reserved

55.6 kHz

010:

Reserved

58.8 kHz

29.4 kHz

011:

60.6 kHz

30.3 kHz

15.2 kHz

100:

30.8 kHz

15.4 kHz

7.7 kHz

101:

15.5 kHz

7.8 kHz

3.9 kHz

110:

7.8 kHz

3.9 kHz

1.9 kHz

111:

Reserved

Serial Bus Interface Data Buffer Register

SBIDBR

(0F91H)

43210

(Initial value: **** ****) R/W

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