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ADE5166 数据表(PDF) 108 Page - Analog Devices |
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ADE5166 数据表(HTML) 108 Page - Analog Devices |
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108 / 148 page  ADE5166/ADE5169/ADE5566/ADE5569 Preliminary Technical Data Rev. PrB | Page 108 of 148 Table 106. Timer 0 High Byte SFR (TH0, 0x8C) Bit Mnemonic Default Description 7 to 0 TH0 0 Timer 0 Data High Byte. Table 107. Timer 0 Low Byte SFR (TL0, 0x8A) Bit Mnemonic Default Description 7 to 0 TL0 0 Timer 0 Data Low Byte. Table 108. Timer 1 High Byte SFR (TH1, 0x8D) Bit Mnemonic Default Description 7 to 0 TH1 0 Timer 1 Data High Byte. Table 109. Timer 1 Low Byte SFR (TL1, 0x8B) Bit Mnemonic Default Description 7 to 0 TL1 0 Timer 1 Data Low Byte. Table 110. Timer 2 High Byte SFR (TH2, 0xCD) Bit Mnemonic Default Description 7 to 0 TH2 0 Timer 2 Data High Byte. Table 111. Timer 2 Low Byte SFR (TL2, 0xCC) Bit Mnemonic Default Description 7 to 0 TL2 0 Timer 2 Data Low Byte. Table 112. Timer 2 Reload/Capture High Byte SFR (RCAP2H, 0xCB) Bit Mnemonic Default Description 7 to 0 TH2 0 Timer 2 Reload/ Capture High Byte. Table 113. Timer 2 Reload/Capture Low Byte SFR (RCAP2L, 0xCA) Bit Mnemonic Default Description 7 to 0 TL2 0 Timer 2 Reload/ Capture Low Byte. TIMER 0 AND TIMER 1 Timer/Counter 0 and Timer/Counter 1 Data Registers Each timer consists of two 8-bit registers. They are Timer 0 high byte SFR (TH0, 0x8C), Timer 0 low byte SFR (TL0, 0x8A), Timer 1 high byte SFR (TH1, 0x8D), and Timer 1 low byte SFR (TL1, 0x8B) These can be used as independent registers or combined into a single 16-bit register, depending on the timer mode configuration (see Table 106 to Table 109). Timer/Counter 0 and Timer/Counter 1 Operating Modes This section describes the operating modes for Timer/Counter 0 and Timer/Counter 1. Unless otherwise noted, these modes of operation are the same for both Timer 0 and Timer 1. Mode 0 (13-Bit Timer/Counter) Mode 0 configures an 8-bit timer/counter. Figure 75 shows Mode 0 operation. Note that the divide-by-12 prescaler is not present on the single cycle core. INTERRUPT TH0 (8 BITS) TL0 (5 BITS) CONTROL TF0 TR0 P0.6/T0 GATE INT0 fCORE C/T0 = 0 C/T0 = 1 Figure 75. Timer/Counter 0, Mode 0 In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the timer overflow flag, TF0. TF0 can then be used to request an interrupt. The counted input is enabled to the timer when TR0 = 1 and either Gate0 = 0 or INT0 = 1. Setting Gate0 = 1 allows the timer to be controlled by the external input INT0 to facilitate pulse width measurements. TR0 is a control bit in the Timer/Counter 0 and Timer/Counter 1 control SFR (TCON, 0x88); the Gate0/Gate1 bits are in Timer/Counter 0 and Timer/Counter 1 mode SFR (TMOD, 0x89). The 13-bit register consists of all eight bits of Timer 0 high byte SFR (TH0, 0x8C) and the lower five bits of Timer 0 low byte SFR (TL0, 0x8A). The upper three bits of TL0 SFR are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. Mode 1 (16-Bit Timer/Counter) Mode 1 is the same as Mode 0 except that the Mode 1 timer register runs with all 16 bits. Mode 1 is shown in Figure 76. GATE fCORE INTERRUPT TH0 (8 BITS) TL0 (8 BITS) CONTROL TF0 TR0 INT0 P0.6/T0 C/T0 = 0 C/T0 = 1 Figure 76. Timer/Counter 0, Mode 1 |
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