ADE5166 datasheet(111/148 Pages) AD

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Preliminary Technical Data

ADE5166/ADE5169/ADE5566/ADE5569

Rev. PrB | Page 111 of 148

PLL

The ADE5166/ADE5169/ADE5566/ADE5569 are intended

for use with a 32.768 kHz watch crystal. A PLL locks onto a

multiple of this frequency to provide a stable 4.096 MHz clock

for the system. The core can operate at this frequency or at

binary submultiples of it to allow power savings when maximum

core performance is not required. The default core clock is the

PLL clock divided by 4, or 1.024 MHz. The ADE energy measure-

ment clock is derived from the PLL clock and is maintained at

4.096 MHz/5 MHz (or 819.2 kHz) across all CD settings.

The PLL is controlled by the CD[2:0] bits in the power control

SFR (POWCON, 0xC5). To protect erroneous changes to the

POWCON SFR, a key is required to modify the register. First,

the key SFR (KYREG, 0xC1) is written with the key, 0xA7, and

then a new value is written to the POWCON SFR.

If the PLL loses lock, the MCU is reset and the PLL_FLT bit is

set in the peripheral configuration SFR (PERIPH, 0xF4). Set the

PLL_FTL_ACK bit in the start ADC measurement SFR

(ADCGO, 0xD8) to acknowledge the PLL fault, clearing the

PLL_FLT bit.

PLL REGISTERS

Table 115. Power Control SFR (POWCON, 0xC5)

Bit

Mnemonic

Default

Description

Reserved

Reserved.

METER_OFF

Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering

functions are not needed in PSM0.

Reserved

This bit should be kept at 0 for proper operation.

COREOFF

Set this bit to shut down the core if in the PSM1 operating mode.

Reserved

Reserved.

2 to 0

CD[2:0]

010

Controls the core clock frequency (fCORE). fCORE = 4.096 MHz/2CD.

CD[2:0]

Result (fCORE in MHz)

000

4.096

001

2.048

010

1.024

011

0.512

100

0.256

101

0.128

110

0.064

111

0.032

Writing to the Power Control SFR (POWCON, 0xC5)

Note that writing data to the POWCON SFR involves writing 0xA7 into the key SFR (KYREG, 0xC1), followed by a write to the

POWCON SFR.

Table 116. Key SFR (KYREG, 0xC1)

Bit

Mnemonic

Default

Description

7 to 0

KYREG

Write 0xA7 to the KYREG SFR before writing to the POWCON SFR to unlock it.

Write 0xEA to the KYREG SFR before writing to the INTPR, HTHSEC, SEC, MIN, or HOUR timekeeping

registers to unlock it.

Table 117. Start ADC Measurement SFR (ADCGO, 0xD8)

Bit

Address

Mnemonic

Default

Description

0xDF

PLL_FTL_ACK

Set this bit to clear the PLL fault bit, PLL_FLT in the PERIPH register. A PLL

fault is generated if a reset was caused because the PLL lost lock.

6 to 3

0xDE to 0xDB

Reserved

Reserved.

0xDA

VDCIN_ADC_GO

Set this bit to initiate an external voltage measurement. This bit is cleared

when the measurement request is received by the ADC.

0xD9

TEMP_ADC_GO

Set this bit to initiate a temperature measurement. This bit is cleared

when the measurement request is received by the ADC.

0xD8

BATT_ADC_GO

Set this bit to initiate a battery measurement. This bit is cleared when the

measurement request is received by the ADC.

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