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ADE5166 数据表(PDF) 138 Page - Analog Devices |
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ADE5166 数据表(HTML) 138 Page - Analog Devices |
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138 / 148 page  ADE5166/ADE5169/ADE5566/ADE5569 Preliminary Technical Data Rev. PrB | Page 138 of 148 I2C-COMPATIBLE INTERFACE The ADE5166/ADE5169/ADE5566/ADE5569 support a fully licensed I2C interface. The I2C interface is implemented as a full hardware master. SDATA is the data I/O pin, and SCLK is the serial clock. These two pins are shared with the MOSI and SCLK pins of the on-chip SPI interface. Therefore, the user can enable only one interface or the other on these pins at any given time. The SCPS bit in the configuration SFR (CFG, 0xAF) selects which peripheral is active. The two pins used for data transfer, SDATA and SCLK, are configured in a wire-AND format that allows arbitration in a multimaster system. The transfer sequence of an I2C system consists of a master device initiating a transfer by generating a start condition while the bus is idle. The master transmits the address of the slave device and the direction of the data transfer in the initial address transfer. If the slave acknowledges, the data transfer is initiated. This continues until the master issues a stop condition and the bus becomes idle. SERIAL CLOCK GENERATION The I2C master in the system generates the serial clock for a transfer. The master channel can be configured to operate in fast mode (256 kHz) or standard mode (32 kHz). The bit rate is defined in the I2CMOD SFR as follows: ] 0 : 1 [ 2 2 16 CR I CORE SCLK f f × = SLAVE ADDRESSES The I2C slave address SFR (I2CADR, 0xE9) contains the slave device ID. The LSB of this register contains a read/write request. A write to this SFR starts the I2C communication. I2C REGISTERS The I2C peripheral interface consists of five SFRs. • I2CMOD • SPI2CSTAT • I2CADR • SPI2CTx • SPI2CRx Because the SPI and I2C serial interfaces share the same pins, they also share the same SFRs, such as the SPI2CTx and SPI2CRx SFRs. In addition, the I2CMOD, I2CADR, and SPI2CSTAT SFRs are shared with the SPIMOD1, SPIMOD2, and SPISTAT SFRs, respectively. Table 150. I2C SFR List SFR Address Mnemonic R/W Length Default Description 0x9A SPI2CTx W 8 SPI/I2C transmit buffer (see Table 145). 0x9B SPI2CRx R 8 0 SPI/I2C receive buffer (see Table 146). 0xE8 I2CMOD R/W 8 0 I2C mode (see Table 151). 0xE9 I2CADR R/W 8 0 I2C slave address (see Table 152). 0xEA SPI2CSTAT R/W 8 0 I2C interrupt status register (see Table 153). Table 151. I2C Mode SFR (I2CMOD, 0xE8) Bit Address Mnemonic Default Description 7 0xEF I2CEN 0 I2C enable bit. When this bit is set to Logic 1, the I2C interface is enabled. A write to the I2CADR SFR starts a communication. 6 to 5 0xEE to 0xED I2CR[1:0] 0 I2C SCLK frequency. I2CR[1:0] Result 00 fCORE/16 = 256 kHz if fCORE = 4.096 MHz. 01 fCORE/32 = 128 kHz if fCORE = 4.096 MHz. 10 fCORE/64 = 64 Hz if fCORE = 4.096 MHz. 11 fCORE/128= 32 kHz if fCORE = 4.096 MHz. 4 to 0 0xEC to 0xE8 I2CRCT[4:0] 0 Configures the length of the I2C received FIFO buffer. The I2C peripheral stops when I2CRCT[4:0] + 1 byte have been read, or if an error occurs. Table 152. I2C Slave Address SFR (I2CADR, 0xE9) Bit Mnemonic Default Description 7 to 1 I2CSLVADR 0 Address of the I2C slave being addressed. Writing to this register starts the I2C transmission (read or write). 0 I2CR_W 0 Command bit for read or write. When this bit is set to Logic 1, a read command is transmitted on the I2C bus. Data from the slave in the SPI2CRx SFR is expected after a command byte. When this bit is set to Logic 0, a write command is transmitted on the I2C bus. Data to slave is expected in the SPI2CTx SFR. |
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