HD64F2149YV datasheet(132/1075 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 3.00 Jan 18, 2006 page 104 of 1044

REJ09B0280-0300

5.1.4

Table 5.2 summarizes the registers of the interrupt controller.

Table 5.2

Interrupt Controller Registers

Name

Abbreviation

R/W

Initial Value

Address*

System control register

SYSCR

R/W

H'09

H'FFC4

IRQ sense control register H

ISCRH

R/W

H'00

H'FEEC

IRQ sense control register L

ISCRL

R/W

H'00

H'FEED

IRQ enable register

IER

R/W

H'00

H'FFC2

IRQ status register

ISR

R/(W)*

H'00

H'FEEB

Keyboard matrix interrupt mask

KMIMR

R/W

H'BF

H'FFF1*

Keyboard matrix interrupt mask

KMIMRA

R/W

H'FF

H'FFF3*

Wakeup event interrupt mask

WUEMRB

R/W

H'FF

H'FE44*

Interrupt control register A

ICRA

R/W

H'00

H'FEE8

Interrupt control register B

ICRB

R/W

H'00

H'FEE9

Interrupt control register C

ICRC

R/W

H'00

H'FEEA

Address break control register

ABRKCR

R/W

H'00

H'FEF4

Break address register A

BARA

R/W

H'00

H'FEF5

Break address register B

BARB

R/W

H'00

H'FEF6

Break address register C

BARC

R/W

H'00

H'FEF7

Notes: 1. Lower 16 bits of the address.

2. Only 0 can be written, for flag clearing.

3. When setting KMIMR and KMIMRA, the HIE bit in SYSCR must be set to 1 and the

MSTP2 bit in MSTPCRL must be cleared to 0.

4. When setting WUEMRB, the MSTP0 bit in MSTPCRL must be cleared to 0.

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