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HD64F2149YV 数据表(PDF) 136 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 136 Page - Renesas Technology Corp |
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136 / 1075 page  Section 5 Interrupt Controller Rev. 3.00 Jan 18, 2006 page 108 of 1044 REJ09B0280-0300 ISCRH Bits 7 to 0, ISCRL Bits 7 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) ISCRH Bits 7 to 0 ISCRL Bits 7 to 0 IRQ7SCB to IRQ0SCB IRQ7SCA to IRQ0SCA Description 0 0 Interrupt request generated at IRQ7 to IRQ0 input low level (Initial value) 1 Interrupt request generated at falling edge of IRQ7 to IRQ0 input 1 0 Interrupt request generated at rising edge of IRQ7 to IRQ0 input 1 Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input 5.2.5 IRQ Status Register (ISR) 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 0 IRQ0F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* Bit Initial value Read/Write Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. |
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