HD64F2149YV datasheet(133/1075 Pages) RENESAS

133 / 1075 page

Section 5 Interrupt Controller

Rev. 3.00 Jan 18, 2006 page 105 of 1044

REJ09B0280-0300

5.2

5.2.1

System Control Register (SYSCR)

CS2E

R/W

IOSE

R/W

INTM1

INTM0

R/W

XRST

RAME

R/W

NMIEG

R/W

HIE

R/W

Bit

Initial value

Read/Write

SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the

detected edge for NMI, among other functions.

Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, System

Control Register (SYSCR).

SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in

software standby mode.

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of four

interrupt control modes for the interrupt controller. The INTM1 bit must not be set to 1.

Bit 5

Bit 4

Interrupt

INTM1

INTM0

Control Mode

Description

Interrupts are controlled by I bit

(Initial value)

Interrupts are controlled by I and UI bits and ICR

Cannot be used in the chip

Bit 2—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.

Bit 2

NMIEG

Description

Interrupt request generated at falling edge of NMI input

(Initial value)

Interrupt request generated at rising edge of NMI input

HD64F2149YV 数据表(PDF) 133 Page - Renesas Technology Corp

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