HD64F2149YV datasheet(137/1075 Pages) RENESAS

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Section 5 Interrupt Controller

Rev. 3.00 Jan 18, 2006 page 109 of 1044

REJ09B0280-0300

Bits 7 to 0—IRQ7 to IRQ0 Flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to

IRQ0 interrupt requests.

Bit n

IRQnF

Description

[Clearing conditions]

(Initial value)

• Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF

• When interrupt exception handling is executed while low-level detection is set

(IRQnSCB = IRQnSCA = 0) and

IRQn input is high*

• When IRQn interrupt exception handling is executed while falling, rising, or both-edge

detection is set (IRQnSCB = 1 or IRQnSCA = 1)*

[Setting conditions]

• When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =

• When a falling edge occurs in IRQn input while falling edge detection is set

(IRQnSCB = 0, IRQnSCA = 1)

• When a rising edge occurs in IRQn input while rising edge detection is set

(IRQnSCB = 1, IRQnSCA = 0)

• When a falling or rising edge occurs in IRQn input while both-edge detection is set

(IRQnSCB = IRQnSCA = 1)

(n = 7 to 0)

Note:

When a product, in which a DTC is incorporated, is used in the following settings, the

corresponding flag bit is not automatically cleared even when exception handing, which

is a clear condition, is executed and the bit is held at 1.

(1)

When DTCEA3 is set to 1(ADI is set to an interrupt source), of IRQ4F flag is not

automatically cleared.

(2)

When DTCEA2 is set to 1(ICIA is set to an interrupt source), clearing of IRQ5F flag

is not automatically cleared.

(3)

When DTCEA1 is set to 1(ICIB is set to an interrupt source), clearing of IRQ6F flag

is not automatically cleared.

(4)

When DTCEA0 is set to 1(OCIA is set to an interrupt source), clearing of IRQ7F

flag is not automatically cleared.

When activation interrupt sources of DTC and IRQ interrupts are used with the above

combinations, clear the interrupt flag by software in the interrupt handling routine of the

corresponding IRQ.

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