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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HD64F2149YV 数据表(PDF) 196 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 196 Page - Renesas Technology Corp |
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196 / 1075 page  Section 7 Data Transfer Controller Rev. 3.00 Jan 18, 2006 page 168 of 1044 REJ09B0280-0300 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Interrupt request Interrupt controller DTC Internal address bus CPU interrupt request On-chip RAM Internal data bus Legend: MRA, MRB: DTC mode registers A and B CRA, CRB: DTC transfer count registers A and B SAR: DTC source address register DAR: DTC destination address register DTCERA to DTCERE: DTC enable registers A to E DTVECR: DTC vector register Figure 7.1 Block Diagram of DTC |
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