HD64F2149YV datasheet(200/1075 Pages) RENESAS

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Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 172 of 1044

REJ09B0280-0300

7.2.2

DTC Mode Register B (MRB)

CHNE

DISEL

—

Bit

Initial value

Read/Write

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

—

Unde-

fined

MRB is an 8-bit register that controls the DTC operating mode.

Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. In chain transfer,

multiple data transfers can be performed consecutively in response to a single transfer request.

With data transfer for which CHNE is set to 1, there is no determination of the end of the specified

number of transfers, clearing of the interrupt source flag, or clearing of DTCER.

Bit 7

CHNE

Description

End of DTC data transfer (activation waiting state is entered)

DTC chain transfer (new register information is read, then data is transferred)

Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are

disabled or enabled after a data transfer.

Bit 6

DISEL

Description

After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is

0 (the DTC clears the interrupt source flag of the activating interrupt to 0)

After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the

interrupt source flag of the activating interrupt to 0)

Bits 5 to 0—Reserved: In the chip these bits have no effect on DTC operation, and should always

be written with 0.

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