HD64F2149YV datasheet(204/1075 Pages) RENESAS

204 / 1075 page

Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 176 of 1044

REJ09B0280-0300

7.2.8

DTC Vector Register (DTVECR)

SWDTE

R/(W)*

DTVEC6

R/W

DTVEC5

R/W

DTVEC4

R/W

DTVEC3

R/W

DTVEC0

R/W

DTVEC2

R/W

DTVEC1

R/W

A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1

is read.

Bit

Initial value

Read/Write

Note: *

DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by

software, and sets a vector number for the software activation interrupt.

DTVECR is initialized to H'00 by a reset and in hardware standby mode.

Bit 7—DTC Software Activation Enable (SWDTE): Specifies enabling or disabling of DTC

software activation. To clear the SWDTE bit by software, read SWDTE when set to 1, then write 0

in the bit.

Bit 7

SWDTE

Description

DTC software activation is disabled

[Clearing condition]

When the DISEL bit is 0 and the specified number of transfers have

not ended

(Initial value)

DTC software activation is enabled

[Holding conditions]

• When data transfer ends with the DISEL bit set to 1

• When the specified number of transfers end

• During software-activated data transfer

Bits 6 to 0—DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits

specify a vector number for DTC software activation.

The vector address is H'0400 + (vector number) << 1 (where << 1 indicates a 1-bit left shift). For

example, if DTVEC6 to DTVEC0 = H'10, the vector address is H'0420.

HD64F2149YV 数据表(PDF) 204 Page - Renesas Technology Corp

HD64F2149YV 数据表(HTML) 204 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载