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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HD64F2149YV 数据表(PDF) 201 Page - Renesas Technology Corp |
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HD64F2149YV 数据表(HTML) 201 Page - Renesas Technology Corp |
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201 / 1075 page  Section 7 Data Transfer Controller Rev. 3.00 Jan 18, 2006 page 173 of 1044 REJ09B0280-0300 7.2.3 DTC Source Address Register (SAR) 23 22 21 20 19 43210 Bit Initial value — Unde- fined Read/write — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 7.2.4 DTC Destination Address Register (DAR) 23 22 21 20 19 43210 Bit Initial value — Unde- fined Read/write — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined — Unde- fined DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. |
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