HD64F2149YV datasheet(274/1075 Pages) RENESAS

274 / 1075 page

Section 8 I/O Ports

Rev. 3.00 Jan 18, 2006 page 246 of 1044

REJ09B0280-0300

8.10.3

Pin Functions

Port 9 pins also function as external interrupt input pins (

IRQ0 to IRQ2), the A/D converter trigger

input pin (

ADTRG), host interface (XBS) input pins (ECS2, CS1, IOW, IOR), the IIC0 I/O pin

(SDA0), the subclock input pin (EXCL), bus control signal I/O pins (

AS/IOS, RD, HWR, LWR,

WAIT), and the system clock (φ) output pin. The pin functions differ between the mode 1, modes

2 and 3 (EXPE = 1) expanded modes and the mode 2 and 3 (EXPE = 0) single-chip modes. The

port 9 pin functions are shown in table 8.19.

Table 8.19

Port 9 Pin Functions

Selection Method and Pin Functions

P97/

WAIT/SDA0

The pin function is switched as shown below according to the combination of

operating mode, bit WMS1 in WSCR, bit ICE in ICCR of IIC0, and bit P97DDR.

Operating

mode

Mode 1,

modes 2 and 3 (EXPE = 1)

Modes 2, 3 (EXPE = 0)

WMS1

—

ICE

—

P97DDR

——

—

Pin function

P97

input

P97

output

SDA0

I/O pin

WAIT

input

P97

input

P97

output

SDA0

I/O pin

When this pin is set as the P97 output pin, it is an NMOS push-pull output.

SDA0 is an NMOS open-drain output, and has direct bus drive capability.

P96/

φ/EXCL

The pin function is switched as shown below according to the combination of

bit EXCLE in LPWRCR and bit P96DDR.

P96DDR

EXCLE

Pin function

P96 input pin

EXCL input pin

φ output pin

When this pin is used as the EXCL input pin, P96DDR should be cleared to 0.

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