AD9520-5SLASHPCBZ datasheet(26/80 Pages) AD

26 / 80 page

AD9520-5

Rev. 0 | Page 26 of 80

THEORY OF OPERATION

OPERATIONAL CONFIGURATIONS

The AD9520 can be configured in several ways. These

configurations must be set up by loading the control registers

(see Table 44 to Table 55). Each section or function must be

individually programmed by setting the appropriate bits in the

corresponding control register or registers. When the desired

configuration is programmed, the user can store these values in

the on-board EEPROM to allow the part to power up in the desired

configuration without user intervention.

Mode 1: Clock Distribution or External VCO < 1600 MHz

When the external clock source to be distributed or the external

VCO/VCXO is <1600 MHz, a configuration that bypasses the

VCO divider can be used. This is the only difference from Mode 2.

Bypassing the VCO divider limits the frequency of the clock

source to <1600 MHz (due to the maximum input frequency

allowed at the channel dividers).

Configuration and Register Settings

For clock distribution applications where the external clock is

<1600 MHz, the register settings shown in Table 19 should be used.

Table 19. Settings for Clock Distribution < 1600 MHz

Description

0x010[1:0] = 01b

PLL asynchronous power-down (PLL off )

0x1E1[0] = 1b

Bypass the VCO divider as the source for

the distribution section

0x1E1[1] = 0b

CLK selected as the source

When using the internal PLL with an external VCO < 1600 MHz,

the PLL must be turned on.

Table 20. Settings for Using Internal PLL with External VCO

< 1600 MHz

Description

0x1E1[0] = 1b

Bypass the VCO divider as the source for

the distribution section

0x010[1:0] = 00b

PLL normal operation (PLL on) along

with other appropriate PLL settings in

0x010 to 0x01E

An external VCO/VCXO requires an external loop filter that

must be connected between CP and the tuning pin of the VCO/

VCXO. This loop filter determines the loop bandwidth and stability

of the PLL. Make sure to select the proper PFD polarity for the

VCO/VCXO being used.

Table 21. Setting the PFD Polarity

Description

0x010[7] = 0b

PFD polarity positive (higher control voltage

produces higher frequency)

0x010[7] = 1b

PFD polarity negative (higher control voltage

produces lower frequency)

AD9520-5/PCBZ 数据表(PDF) 26 Page - Analog Devices

AD9520-5/PCBZ 数据表(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载

链接网址

AD9520-5/PCBZ 数据表(PDF) 26 Page - Analog Devices

AD9520-5/PCBZ 数据表(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表 下载

链接网址

数据表下载