AD9520-5SLASHPCBZ datasheet(64/80 Pages) AD

64 / 80 page

AD9520-5

Rev. 0 | Page 64 of 80

Reg.

Addr

(Hex) Bit(s) Name

Description

[7]

[6]

[5]

[4]

[3]

[2]

Level or

Dynamic

Signal

Signal at STATUS Pin

DYN

Unselected reference to PLL (not available when in

differential mode).

LVL

Status of selected reference (status of differential reference);

active low.

LVL

Status of unselected reference (not available in differential

mode); active low.

LVL

Status of REF1 frequency (active low).

LVL

Status of REF2 frequency (active low).

LVL

(Status of REF1 frequency) AND (status of REF2 frequency).

LVL

(DLD) AND (Status of selected reference) AND (status of VCO).

LVL

Status of CLK frequency (active low).

LVL

Selected reference (low = REF2, high = REF1).

LVL

DLD (active low).

LVL

Holdover active (active low).

LVL

LD pin comparator output (active low).

017

[1:0]

Antibacklash

pulse width

[1]

[0]

Antibacklash Pulse Width (ns)

2.9 (default)

1.3

6.0

2.9

018

[7]

Enable CMOS

reference input

dc offset

Enables dc offset in single-ended CMOS input mode to prevent chattering when ac-coupled and input is lost.

[7] = 0; disable dc offset (default).

[7] = 1; enable dc offset.

018

[6:5]

Lock detect

counter

Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates

a locked condition.

[6]

[5]

PFD Cycles to Determine Lock

5 (default)

255

018

[4]

Digital lock

detect window

If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time,

the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock

threshold.

[4] = 0; high range (default).

[4] = 1; low range.

018

[3]

Disable digital

lock detect

Digital lock detect operation.

[3] = 0; normal lock detect operation (default).

[3] = 1; disable lock detect.

019

[7:6]

R, A, B counters

SYNC pin reset

[7]

[6]

Action

Do nothing on SYNC (default).

Asynchronous reset.

Synchronous reset.

Do nothing on SYNC.

019

[5:3]

R path delay

R path delay, see Table 2 (default: 0x0).

019

[2:0]

N path delay

N path delay, see Table 2 (default: 0x0).

AD9520-5/PCBZ 数据表(PDF) 64 Page - Analog Devices

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