AD9520-5SLASHPCBZ datasheet(70/80 Pages) AD

70 / 80 page

AD9520-5

Rev. 0 | Page 70 of 80

Reg.

Addr

(Hex) Bit(s) Name

Description

0FC

[6]

CSDLD En OUT6 OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[5]

CSDLD En OUT5 OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[4]

CSDLD En OUT4 OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[3]

CSDLD En OUT3 OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[2]

CSDLD En OUT2 OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[1]

CSDLD En OUT1 OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FC

[0]

CSDLD En OUT0 OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FD

[3]

CSDLD En

OUT11

OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FD

[2]

CSDLD En

OUT10

OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FD

[1]

CSDLD En OUT9 OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

0FD

[0]

CSDLD En OUT8 OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].

Table 50. LVPECL Channel Dividers

Reg.

Addr

(Hex) Bit(s) Name

Description

190

[7:4]

Divider 0 low cycles

Number of clock cycles (minus 1) of the divider input during which the divider output stays

low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).

190

[3:0]

Divider 0 high cycles

Number of clock cycles (minus 1) of the divider input during which the divider output stays

high. A value of 0x7 means that the divider is high for eight input clock cycles (default: 0x7).

191

[7]

Divider 0 bypass

Bypasses and powers down the divider; routes input to divider output.

[7] = 0; use divider (default).

[7] = 1; bypass divider.

191

[6]

Divider 0 ignore SYNC

Ignore SYNC.

[6] = 0; obey chip-level SYNC signal (default).

[6] = 1; ignore chip-level SYNC signal.

191

[5]

Divider 0 force high

Forces divider output to high. This requires that ignore SYNC also be set.

[5] = 0; divider output forced to low (default).

[5] = 1; divider output forced to high.

191

[4]

Divider 0 start high

Selects clock output to start high or start low.

[4] = 0; start low (default).

[4] = 1; start high.

191

[3:0]

Divider 0 phase offset

Phase offset (default: 0x0).

192

[2]

Channel 0 power-down

Channel 0 powers down.

[2] = 0; normal operation (default).

[2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into safe power-

down mode by setting this bit.)

192

[1]

Channel 0 direct-to-output

Connects OUT0, OUT1, and OUT2 to Divider 0 or directly to CLK.

[1] = 0; OUT0, OUT1, and OUT2 are connected to Divider 0 (default).

[1] = 1;

If 0x1E1[0] = 0, the CLK is routed directly to OUT0, OUT1, and OUT2.

If 0x1E1[0] = 1, there is no effect.

192

[0]

Disable Divider 0 DCC

Duty-cycle correction function.

[0] = 0; enable duty-cycle correction (default).

[0] = 1; disable duty-cycle correction.

AD9520-5/PCBZ 数据表(PDF) 70 Page - Analog Devices

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