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AD9520-5/PCBZ 数据表(PDF) 27 Page - Analog Devices

部件名 AD9520-5/PCBZ
功能描述  12 LVPECL/24 CMOS Output Clock Generator
PDF  80 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9520-5/PCBZ 数据表(HTML) 27 Page - Analog Devices

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AD9520-5
Rev. 0 | Page 27 of 80
PROGRAMMABLE
N DELAY
REFIN
CLK
CLK
REF1
REF2
BUF
AMP
AD9520-5
STATUS
REFERENCE
SWITCHOVER
REF_SEL
CPRSET VCP
VS
GND
RSET
DISTRIBUTION
REFERENCE
REFMON
CP
STATUS
LD
P, P + 1
PRESCALER
A/B
COUNTERS
N DIVIDER
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
CHARGE
PUMP
HOLD
0
1
DIVIDE BY 1,
2, 3, 4, 5, OR 6
PD
SYNC
REFIN
RESET
EEPROM
DIGITAL
LOGIC
EEPROM
DIVIDE BY
1 TO 32
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
DIVIDE BY
1 TO 32
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
DIVIDE BY
1 TO 32
OUT6
OUT6
OUT7
OUT7
OUT8
OUT8
DIVIDE BY
1 TO 32
OUT9
OUT9
OUT10
OUT10
OUT11
OUT11
ZERO DELAY BLOCK
STATUS
STATUS
SP1
SP0
SPI
INTERFACE
I2C
INTERFACE
SCLK/SCL
SDIO/SDA
SDO
CS
SERIAL
PORT
DECODE
VS_DRV
OPTIONAL
Figure 26. Clock Distribution or External VCO < 1600 MHz (Mode 1)



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