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AD9520-5/PCBZ 数据表(PDF) 56 Page - Analog Devices |
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AD9520-5/PCBZ 数据表(HTML) 56 Page - Analog Devices |
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56 / 80 page  AD9520-5 Rev. 0 | Page 56 of 80 REGISTER MAP Register addresses that are not listed in Table 44 are not used, and writing to those registers has no effect. The user should avoid writing values other than 00h to register addresses marked unused. Table 44. Register Map Overview Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Serial Port Configuration 000 Serial port config (SPI mode) SDO active LSB first/ addr incr Soft reset (self- clearing) Unused Unused Soft reset (self- clearing) LSB first/ addr incr SDO active 00 Serial port config (I²C mode) Unused Soft reset (self- clearing) Unused Unused Soft reset (self- clearing) Unused 00 001 Unused N/A 002 Reserved (read-only) N/A 003 Reserved (read-only) N/A 004 Readback control Unused Readback active regs 00 EEPROM ID 005 EEPROM customer version ID EEPROM customer version ID (LSB) 00 006 EEPROM customer version ID (MSB) 00 007 to 00F Unused 00 PLL 010 PFD charge pump PFD polarity Charge pump current Charge pump mode PLL power-down 7D 011 R counter 14-bit R counter, Bits[7:0] (LSB) 01 012 Unused 14-bit R counter, Bits[13:8] (MSB) 00 013 A counter Unused 6-bit A counter 00 014 B counter 13-bit B counter, Bits[7:0] (LSB) 03 015 Unused 13-bit B counter, Bits[12:8] (MSB) 00 016 PLL_CTRL_1 Set CP pin to VCP/2 Reset R counter Reset A and B counters Reset all counters B counter bypass Prescaler P 06 017 PLL_CTRL_2 STATUS pin control Antibacklash pulse width 00 018 PLL_CTRL_3 Enable CMOS reference input dc offset Lock detect counter Digital lock detect window Disable digital lock detect Unused 06 019 PLL_CTRL_4 R, A, B counters SYNC pin reset R path delay N path delay 00 01A PLL_CTRL_5 Enable STATUS pin divider Ref freq monitor threshold LD pin control 00 01B PLL_CTRL_6 Enable CLK frequency monitor Enable REF2 (REFIN) frequency monitor Enable REF1 (REFIN) frequency monitor REFMON pin control 00 01C PLL_CTRL_7 Disable switchover deglitch Select REF2 Use REF_SEL pin Enable automatic reference switchover Stay on REF2 Enable REF2 Enable REF1 Enable differential reference 00 01D PLL_CTRL_8 Enable Status_EEPROM at STATUS pin Enable XTAL OSC Enable clock doubler Disable PLL status register Enable LD pin comparator Unused Enable external holdover Enable holdover 80 |
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