AD9520-5SLASHPCBZ datasheet(5/80 Pages) AD

5 / 80 page

AD9520-5

Rev. 0 | Page 5 of 80

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CHARGE PUMP (CP)

ICP Sink/Source

Programmable

High Value

4.8

With CPRSET = 5.1 kΩ; higher ICP is possible by

changing CPRSET

Low Value

0.60

With CPRSET = 5.1 kΩ; lower ICP is possible by

changing CPRSET

Absolute Accuracy

2.5

Charge pump voltage set to VCP/2

CPRSET Range

2.7

kΩ

ICP High Impedance Mode Leakage

Sink-and-Source Current Matching

0.5 V < VCP < VCP − 0.5 V; VCP is the voltage on the CP (charge

pump) pin; VCP is the voltage on the VCP power supply pin

ICP vs. VCP

1.5

0.5 V < VCP < VCP − 0.5 V

ICP vs. Temperature

VCP = VCP/2 V

PRESCALER (PART OF N DIVIDER)

Prescaler Input Frequency

P = 1 FD

300

MHz

P = 2 FD

600

MHz

P = 3 FD

900

MHz

P = 2 DM (2/3)

600

MHz

P = 4 DM (4/5)

1000

MHz

P = 8 DM (8/9)

2400

MHz

P = 16 DM (16/17)

3000

MHz

P = 32 DM (32/33)

3000

MHz

Prescaler Output Frequency

300

MHz

A, B counter input frequency (prescaler input

frequency divided by P)

PLL N DIVIDER DELAY

000

Off

001

410

010

530

011

650

100

770

101

890

110

1010

111

1130

PLL R DIVIDER DELAY

000

Off

001

370

010

490

011

610

100

730

101

850

110

970

111

1090

PHASE OFFSET IN ZERO DELAY

REF refers to REFIN (REF1)/REFIN (REF2)

Phase Offset (REF-to-LVPECL Clock Output

Pins) in Internal Zero Delay Mode

560

1060

1310

When N delay and R delay are bypassed

Phase Offset (REF-to-LVPECL Clock Output

Pins) in Internal Zero Delay Mode

−320

+50

+240

When N delay = Setting 110 and R delay is bypassed

AD9520-5/PCBZ 数据表(PDF) 5 Page - Analog Devices

AD9520-5/PCBZ 数据表(HTML) 5 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载