AD9520-5SLASHPCBZ datasheet(38/80 Pages) AD

38 / 80 page

AD9520-5

Rev. 0 | Page 38 of 80

DIVIDE BY 1,

2, 3, 4, 5, OR 6

EXTERNAL VCXO

CLK/CLK

DIVIDER

DELAY

DIVIDER

DELAY

PFD

MUX1

REG 0x01E[1] = 1

REFIN/

REFIN

INTERNAL ZERO DELAY CLOCK FEEDBACK PATH

CHANNEL DIVIDER 0

CHANNEL DIVIDER 1

CHANNEL DIVIDER 2

CHANNEL DIVIDER 3

OUT0 TO OUT2

OUT3 TO OUT5

OUT6 TO OUT8

OUT9 TO OUT11

AD9520-5

LOOP

FILTER

Figure 36. Zero Delay Function

ZERO DELAY OPERATION

Zero delay operation aligns the phase of the output clocks with

the phase of the external PLL reference input.

The zero delay function of the AD9520-5 is achieved by feeding

the output of Channel Divider 0 back to the PLL N divider. In

Figure 36, the change in signal routing for zero delay mode is

shown in blue.

Set Register 0x01E[1] = 1b to select zero delay mode. In the zero

delay mode, the output of Channel Divider 0 is routed back to the

PLL (N divider) through Mux1 (feedback path shown in blue in

Figure 36). The PLL synchronizes the phase/edge of the output of

Channel Divider 0 with the phase/edge of the reference input.

Because the channel dividers are synchronized to each other,

the outputs of the channel divider are synchronous with the

reference input. Both the R delay and the N delay inside the

PLL can be programmed to compensate for the propagation

delay from the output drivers and PLL components to minimize

the phase offset between the clock output and the reference

input to achieve zero delay.

AD9520-5/PCBZ 数据表(PDF) 38 Page - Analog Devices

AD9520-5/PCBZ 数据表(HTML) 38 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载