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AD9520-5/PCBZ 数据表(PDF) 57 Page - Analog Devices |
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AD9520-5/PCBZ 数据表(HTML) 57 Page - Analog Devices |
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57 / 80 page  AD9520-5 Rev. 0 | Page 57 of 80 Addr (Hex) Parameter Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) 01E PLL_CTRL_9 Unused Enable zero delay Unused 00 01F PLL_Readback (read-only) Unused Holdover active REF2 selected CLK freq > threshold REF2 freq > threshold REF1 freq > threshold Digital lock detect N/A Output Driver Control 0F0 OUT0 control OUT0 format OUT0 CMOS configuration OUT0 polarity OUT0 LVPECL differential voltage OUT0 LVPECL power-down 64 0F1 OUT1 control OUT1 format OUT1 CMOS configuration OUT1 polarity OUT1 LVPECL differential voltage OUT1 LVPECL power-down 64 0F2 OUT2 control OUT2 format OUT2 CMOS configuration OUT2 polarity OUT2 LVPECL differential voltage OUT2 LVPECL power-down 64 0F3 OUT3 control OUT3 format OUT3 CMOS configuration OUT3 polarity OUT3 LVPECL differential voltage OUT3 LVPECL power-down 64 0F4 OUT4 control OUT4 format OUT4 CMOS configuration OUT4 polarity OUT4 LVPECL differential voltage OUT4 LVPECL power-down 64 0F5 OUT5 control OUT5 format OUT5 CMOS configuration OUT5 polarity OUT5 LVPECL differential voltage OUT5 LVPECL power-down 64 0F6 OUT6 control OUT6 format OUT6 CMOS configuration OUT6 polarity OUT6 LVPECL differential voltage OUT6 LVPECL power-down 64 0F7 OUT7 control OUT7 format OUT7 CMOS configuration OUT7 polarity OUT7 LVPECL differential voltage OUT7 LVPECL power-down 64 0F8 OUT8 control OUT8 format OUT8 CMOS configuration OUT8 polarity OUT8 LVPECL differential voltage OUT8 LVPECL power-down 64 0F9 OUT9 control OUT9 format OUT9 CMOS configuration OUT9 polarity OUT9 LVPECL differential voltage OUT9 LVPECL power-down 64 0FA OUT10 control OUT10 format OUT10 CMOS configuration OUT10 polarity OUT10 LVPECL differential voltage OUT10 LVPECL power-down 64 0FB OUT11 control OUT11 format OUT11 CMOS configuration OUT11 polarity OUT11 LVPECL differential voltage OUT11 LVPECL power-down 64 0FC Enable output on CSDLD CSDLD En OUT7 CSDLD En OUT6 CSDLD En OUT5 CSDLD En OUT4 CSDLD En OUT3 CSDLD En OUT2 CSDLD En OUT1 CSDLD En OUT0 00 0FD Enable output on CSDLD Unused CSDLD En OUT11 CSDLD En OUT10 CSDLD En OUT9 CSDLD En OUT8 00 0FE to 18F Unused 00 LVPECL Channel Dividers 190 Divider 0 (PECL) Divider 0 low cycles Divider 0 high cycles 77 191 Divider 0 bypass Divider 0 ignore SYNC Divider 0 force high Divider 0 start high Divider 0 phase offset 00 192 Unused Channel 0 power- down Channel 0 direct-to- output Disable Divider 0 DCC 00 |
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