AD9520-5SLASHPCBZ datasheet(31/80 Pages) AD

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AD9520-5

Rev. 0 | Page 31 of 80

PLL External Loop Filter

An example of an external loop filter for the PLL is shown in

Figure 29. A loop filter must be calculated for each desired PLL

configuration. The values of the components depend on the VCO

frequency, the KVCO, the PFD frequency, the charge pump current,

the desired loop bandwidth, and the desired phase margin. The

loop filter affects the phase noise, the loop settling time, and the

loop stability. A basic knowledge of PLL theory is necessary for

understanding loop filter design. ADIsimCLK can help with the

calculation of a loop filter according to the application requirements.

CLK/CLK

EXTERNAL

VCO/VCXO

CHARGE

PUMP

AD9520-5

Figure 29. Example of External Loop Filter for PLL

PLL Reference Inputs

The AD9520 features a flexible PLL reference input circuit that

allows a fully differential input, two separate single-ended inputs,

or a 16.67 MHz to 33.33 MHz crystal oscillator with an on-chip

maintaining amplifier. An optional reference clock doubler

can be used to double the PLL reference frequency. The input

frequency range for the reference inputs is specified in Table 2.

Both the differential and the single-ended inputs are self-biased,

allowing for easy ac coupling of input signals.

Either a differential or a single-ended reference must be specifically

enabled. All PLL reference inputs are off by default.

The differential input and the single-ended inputs share two pins,

REFIN (REF1) and REFIN (REF2). The desired reference input

type is selected and controlled by 0x01C (see

and

Table 44

Table 48

When the differential reference input is selected, the self-bias

level of the two sides is offset slightly to prevent chattering of

the input buffer when the reference is slow or missing. The

specification for this voltage level can be found in Table 2.

The input hysteresis increases the voltage swing required of

the driver to overcome the offset.

The single-ended inputs can be driven by either a dc-coupled

CMOS level signal or an ac-coupled sine wave or square wave. To

avoid input buffer chatter when a single-ended, ac-coupled input

signal stops toggling, the user can set 0x018[7] to 1b. This shifts the

dc offset bias point down 140 mV. To increase isolation and reduce

power, each single-ended input can be independently powered down.

The differential reference input receiver is powered down when

the differential reference input is not selected or when the PLL

is powered down. The single-ended buffers power down when

the PLL is powered down or when their respective individual

power-down registers are set. When the differential mode is

selected, the single-ended inputs are powered down.

In differential mode, the reference input pins are internally self-

biased so that they can be ac-coupled via capacitors. It is possible to

dc couple to these inputs. If the differential REFIN is driven by

a single-ended signal, the unused side (REFIN) should be

decoupled via a suitable capacitor to a quiet ground.

shows the equivalent circuit of REFIN.

Figure 30

REF1

REF2

REFIN

150Ω

10kΩ

12kΩ

10kΩ

REFIN

85kΩ

Figure 30. REFIN Equivalent Circuit for Non-XTAL Mode

Crystal mode is nearly identical to differential mode. The user

enables a maintaining amplifier by setting the Enable XTAL

OSC bit, and putting a series resonant, AT fundamental cut

crystal across the REFIN/REFIN pins.

Reference Switchover

The AD9520 supports dual single-ended CMOS inputs, as well

as a single differential reference input. In the dual single-ended

reference mode, the AD9520 supports automatic and manual

PLL reference clock switching between REF1 (on Pin REFIN)

and REF2 (on Pin REFIN). This feature supports networking

and other applications that require redundant references.

The AD9520 features a dc offset option in single-ended mode.

This option is designed to eliminate the risk of the reference

inputs chattering when they are ac-coupled and the reference

clock disappears. When using the reference switchover, the

single-ended reference inputs should be dc-coupled CMOS

levels (with the AD9520 dc offset feature disabled). Alternatively,

the inputs can be ac-coupled and the dc offset feature enabled.

The user should keep in mind, however, that the minimum

input amplitude for the reference inputs is greater when the dc

offset is turned on.

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