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AD9520-5/PCBZ 数据表(PDF) 69 Page - Analog Devices |
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AD9520-5/PCBZ 数据表(HTML) 69 Page - Analog Devices |
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69 / 80 page  AD9520-5 Rev. 0 | Page 69 of 80 Table 49. Output Driver Control Reg. Addr (Hex) Bit(s) Name Description 0F0 [7] OUT0 format Selects the output type for OUT0. [7] = 0; LVPECL (default). [7] = 1; CMOS. 0F0 [6:5] OUT0 CMOS configuration Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1. [6:5] OUT0A OUT0B 00 Tristate Tristate 01 On Tristate 10 Tristate On 11 (default) On On 0F0 [4:3] OUT0 polarity Sets the output polarity for OUT0. [7] [4] [3] Output Type OUT0A OUT0B 0 (default) X 0 (default) LVPECL Noninverting Inverting 0 X 1 LVPECL Inverting Noninverting 1 0 (default) 0 CMOS Noninverting Noninverting 1 0 1 CMOS Inverting Inverting 1 1 0 CMOS Noninverting Inverting 1 1 1 CMOS Inverting Noninverting 0F0 [2:1] OUT0 LVPECL differential voltage Sets the LVPECL output differential voltage (VOD). [2] [1] VOD (mV) 0 0 400 0 1 600 1 (default) 0 (default) 780 1 1 960 0F0 [0] OUT0 LVPECL power-down LVPECL power-down. [0] = 0; normal operation (default). [0] = 1; safe power-down. 0F1 [7:0] OUT1 control This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0. 0F2 [7:0] OUT2 control This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0. 0F3 [7:0] OUT3 control This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0. 0F4 [7:0] OUT4 control This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0. 0F5 [7:0] OUT5 control This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0. 0F6 [7:0] OUT6 control This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0. 0F7 [7:0] OUT7 control This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0. 0F8 [7:0] OUT8 control This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0. 0F9 [7:0] OUT9 control This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0. 0FA [7:0] OUT10 control This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0. 0FB [7:0] OUT11 control This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0. 0FC [7] CSDLD En OUT7 OUT7 is enabled only if CSDLD is high. [7] CSDLD Signal OUT7 Enable Status 0 0 Not affected by CSDLD signal (default). 1 0 Asynchronous power-down. 1 1 Asynchronously enable OUT7 if not powered down by other settings. To use this feature, the user must use current source digital lock detect and set the enable LD pin comparator bit (0x01D[3]). |
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