AD9520-5SLASHPCBZ datasheet(68/80 Pages) AD

68 / 80 page

AD9520-5

Rev. 0 | Page 68 of 80

Reg.

Addr

(Hex) Bit(s) Name

Description

01D

[5]

Enable clock

doubler

Enable PLL reference input clock doubler.

[5] = 0; doubler disabled (default).

[5] = 1; doubler enabled.

01D

[4]

Disable PLL

status register

Disables the PLL status register readback.

[4] = 0; PLL status register enabled (default).

[4] = 1; PLL status register disabled. If this bit is set, Register 01F is not automatically updated.

01D

[3]

Enable LD pin

comparator

Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.

When the AD9520 is in internal (automatic) holdover mode, this enables the use of the voltage on the

LD pin to determine if the PLL was previously in a locked state (see Figure 34). Otherwise, this can be used

with the REFMON and STATUS pins to monitor the voltage on the LD pin.

[3] = 0; disable LD pin comparator and ignore the LD pin voltage; internal/automatic holdover

controller treats this pin as true (high, default).

[3] = 1; enable LD pin comparator (use LD pin voltage to determine if the PLL was previously locked).

01D

[1]

Enable external

holdover

Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)

[1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default).

[1] = 1; external holdover mode, holdover controlled by SYNC pin.

01D

[0]

Enable

holdover

Enables the internally controlled holdover function.

[0] = 0; holdover disabled (default).

[0] = 1; holdover enabled.

01E

[1]

Enable zero

delay

Enables zero delay function.

[1] = 0; disables zero delay function (default).

[1] = 1; enables zero delay function.

01F

[5]

Holdover active

(read-only)

Readback register. Indicates if the part is in the holdover state (see Figure 34). This is not the same as

holdover enabled.

[5] = 0; not in holdover.

[5] = 1; holdover state active.

01F

[4]

REF2 selected

(read-only)

Readback register. Indicates which PLL reference is selected as the input to the PLL.

[4] = 0; REF1 selected (or differential reference if in differential mode).

[4] = 1; REF2 selected.

01F

[3]

CLK frequency

> threshold

(read-only)

Readback register. Indicates if the external CLK input frequency is greater than the threshold (see Table 14,

REF1, REF2, and external CLK frequency status monitor parameter).

[3] = 0; the external CLK frequency is less than the threshold.

[3] = 1; the external CLK frequency is greater than the threshold.

01F

[2]

REF2 frequency

> threshold

(read-only)

Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency

set by Register 0x01A[6].

[2] = 0; REF2 frequency is less than the threshold frequency.

[2] = 1; REF2 frequency is greater than the threshold frequency.

01F

[1]

REF1 frequency

> threshold

(read-only)

Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency

set by Register 0x01A[6].

[1] = 0; REF1 frequency is less than the threshold frequency.

[1] = 1; REF1 frequency is greater than the threshold frequency.

01F

[0]

Digital lock

detect

(read-only)

Readback register. Digital lock detect.

[0] = 0; PLL is not locked.

[0] = 1; PLL is locked.

AD9520-5/PCBZ 数据表(PDF) 68 Page - Analog Devices

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