AD9520-5SLASHPCBZ datasheet(36/80 Pages) AD

36 / 80 page

AD9520-5

Rev. 0 | Page 36 of 80

YES

PLL ENABLED

DLD == LOW

WAS

LD PIN == HIGH

WHEN DLD WENT

LOW?

HIGH IMPEDANCE

CHARGE PUMP

REFERENCE

EDGE AT PFD?

RELEASE

CHARGE PUMP

HIGH IMPEDANCE

DLD == HIGH

LOOP OUT OF LOCK. DIGITAL LOCK

DETECT SIGNAL GOES LOW WHEN THE

LOOP LEAVES LOCK AS DETERMINED

BY THE PHASE DIFFERENCE AT THE

INPUT OF THE PFD.

ANALOG LOCK DETECT PIN INDICATES

LOCK WAS PREVIOUSLY ACHIEVED.

(0x01D[3] = 1; USE LD PIN VOLTAGE

WITH HOLDOVER.

0x01D[3] = 0; IGNORE LD PIN VOLTAGE,

TREAT LD PIN AS ALWAYS HIGH.)

CHARGE PUMP IS MADE

HIGH IMPEDANCE.

PLL COUNTERS CONTINUE

OPERATING NORMALLY.

CHARGE PUMP REMAINS HIGH

IMPEDANCE UNTIL THE REFERENCE

RETURNS.

TAKE CHARGE PUMP OUT OF

HIGH IMPEDANCE. PLL CAN

NOW RESETTLE.

WAIT FOR DLD TO GO HIGH. THIS TAKES

5 TO 255 CYCLES (PROGRAMMING OF THE DLD

DELAY COUNTER) WITH THE REFERENCE AND

FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT

THE PFD. THIS ENSURES THAT THE HOLDOVER

FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK

BEFORE THE HOLDOVER FUNCTION CAN BE

RETRIGGERED.

YES

Figure 34. Flowchart of Automatic/Internal Holdover Mode

The holdover function senses the logic level of the LD pin as a

condition to enter holdover. The signal at LD can be from the

DLD, ALD, or current source LD mode (CSDLD). It is possible

to disable the LD comparator (0x01D[3]), which causes the

holdover function to always sense LD as being high. If DLD is

used, it is possible for the DLD signal to chatter while the PLL is

reacquiring lock. The holdover function may retrigger, thereby

preventing the holdover mode from terminating. Use of the

current source lock detect mode is recommended to avoid this

situation (see the Current Source Digital Lock Detect (CSDLD)

section).

When in holdover mode, the charge pump stays in a high

impedance state as long as there is no reference clock present.

As in the external holdover mode, the B counter (in the N divider)

is reset synchronously with the charge pump leaving the high

impedance state on the reference path PFD event. This helps

align the edges out of the R and N dividers for faster settling of

the PLL and reduces frequency errors during settling. Because

the prescaler is not reset, this feature works best when the B and

R numbers are close because this results in a smaller phase

difference for the loop to settle out.

AD9520-5/PCBZ 数据表(PDF) 36 Page - Analog Devices

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