AD9520-5SLASHPCBZ datasheet(34/80 Pages) AD

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AD9520-5

Rev. 0 | Page 34 of 80

Analog Lock Detect (ALD)

The AD9520 provides an ALD function that can be selected for

use at the LD pin. There are two operating modes for ALD:

•

N-channel open-drain lock detect. This signal requires a

pull-up resistor to the positive supply, VS. The output is

normally high with short, low going pulses. Lock is indicated

by the minimum duty cycle of the low going pulses.

•

P-channel open-drain lock detect. This signal requires a

pull-down resistor to GND. The output is normally low with

short, high going pulses. Lock is indicated by the minimum

duty cycle of the high going pulses.

The analog lock detect function requires an RC filter to provide a

logic level indicating lock/unlock. The ADIsimCLK tool can be

used to help the user select the right passive component values

for ALD to ensure its correct operation.

AD9520

ALD

VOUT

VS = 3.3V

Figure 31. Example of Analog Lock Detect Filter Using

N-Channel Open-Drain Driver

Current Source Digital Lock Detect (CSDLD)

During the PLL locking sequence, it is normal for the DLD

signal to toggle a number of times before remaining steady

when the PLL is completely locked and stable. There may be

applications where it is desirable to have DLD asserted only

after the PLL is solidly locked. This is possible by using the

current source digital lock detect function.

The current source lock detect provides a current of 110 μA when

DLD is true and shorts to ground when DLD is false. If a capacitor

is connected to the LD pin, it charges at a rate determined by the

current source during the DLD true time but is discharged nearly

instantly when DLD is false. By monitoring the voltage at the

LD pin (top of the capacitor), LD = high happens only after the

DLD is true for a sufficiently long time. Any momentary DLD

false resets the charging. By selecting a properly sized capacitor,

it is possible to delay a lock detect indication until the PLL is

stably locked and the lock detect does not chatter.

To use current source digital lock detect, do the following:

•

Place a capacitor to ground on the LD pin

•

Set 0x01A[5:0] = 0x04

•

Enable the LD pin comparator (0x01D[3] = 1)

The LD pin comparator senses the voltage on the LD pin, and

the comparator output can be made available at the REFMON

pin control (0x01B[4:0]) or the STATUS pin control (0x017[7:2]).

The internal LD pin comparator trip point and hysteresis are given

in Table 14. The voltage on the capacitor can also be sensed by

an external comparator connected to the LD pin. In this case,

enabling the on-board LD pin comparator is not necessary.

The user can asynchronously enable individual clock outputs only

when CSDLD is high. To enable this feature, set the appropriate bits

in the enable output on the CSDLD registers (0x0FC and 0x0FD).

AD9520

REFMON

STATUS

VOUT

110µA

DLD

LD PIN

COMPARATOR

Figure 32. Current Source Digital Lock Detect

External VCXO/VCO Clock Input (CLK/CLK)

This differential input is used to drive the AD9520 clock

distribution section. This input can receive up to 2.4 GHz.

The pins are internally self-biased, and the input signal should

be ac-coupled via capacitors.

CLOCK INPUT

STAGE

CLK

5kΩ

2.5kΩ

Figure 33. CLK Equivalent Input Circuit

The CLK/CLK input can be used either as a distribution only

input (with the PLL off) or as a feedback input for an external

VCO/VCXO using the internal PLL.

Holdover

The AD9520 PLL has a holdover function. Holdover is

implemented by placing the charge pump in a high impedance

state. This function is useful when the PLL reference clock is

lost. Holdover mode allows the external VCO to maintain a

relatively constant frequency even though there is no reference

clock. Without this function, the charge pump is placed into a

constant pump-up or pump-down state, resulting in a massive

VCO frequency shift. Because the charge pump is placed in a

high impedance state, any leakage that occurs at the charge

pump output or the VCO tuning node causes a drift of the VCO

frequency. This can be mitigated by using a loop filter that

contains a large capacitive component because this drift is

limited by the current leakage induced slew rate (ILEAK/C) of

the VCO control voltage.

Both a manual holdover mode, using the SYNC pin, and an

automatic holdover mode are provided. To use either function, the

holdover function must be enabled (0x01D[0]).

AD9520-5/PCBZ 数据表(PDF) 34 Page - Analog Devices

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