AD9520-5SLASHPCBZ datasheet(35/80 Pages) AD

35 / 80 page

AD9520-5

Rev. 0 | Page 35 of 80

External/Manual Holdover Mode

A manual holdover mode can be enabled that allows the user to

place the charge pump into a high impedance state when the

SYNC pin is asserted low. This operation is edge sensitive, not

level sensitive. The charge pump enters a high impedance state

immediately. To take the charge pump out of a high impedance

state, take the SYNC pin high. The charge pump then leaves the

high impedance state synchronously with the next PFD rising

edge from the reference clock. This prevents extraneous charge

pump events from occurring during the time between SYNC

going high and the next PFD event. This also means that the

charge pump stays in a high impedance state if there is no

reference clock present.

The B counter (in the N divider) is reset synchronously with the

charge pump, leaving the high impedance state on the reference

path PFD event. This helps align the edges out of the R and N

dividers for faster settling of the PLL. Because the prescaler is

not reset, this feature works best when the B and R numbers are

close because this results in a smaller phase difference for the

loop to settle out.

When using this mode, the channel dividers should be set to ignore

the SYNC pin (at least after an initial SYNC event). If the dividers

are not set to ignore the SYNC pin, any time SYNC is taken low

to put the part into holdover, the distribution outputs turn off.

The channel divider ignore SYNC function is found in 0x191[6],

0x194[6], 0x197[6], and 0x19A[6] for Channel Divider 0, Channel

Divider 1, Channel Divider 2, and Channel Divider 3, respectively.

Automatic/Internal Holdover Mode

When enabled, this function automatically puts the charge

pump into a high impedance state when the loop loses lock.

The assumption is that the only reason the loop loses lock is due

to the PLL losing the reference clock; therefore, the holdover

function puts the charge pump into a high impedance state to

maintain the VCO frequency as close as possible to the original

frequency before the reference clock disappeared.

A flowchart of the automatic/internal holdover function

operation is shown in Figure 34.

AD9520-5/PCBZ 数据表(PDF) 35 Page - Analog Devices

AD9520-5/PCBZ 数据表(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载