AD9520-5SLASHPCBZ datasheet(43/80 Pages) AD

43 / 80 page

AD9520-5

Rev. 0 | Page 43 of 80

910

INPUT TO VCO DIVIDER

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 39. SYNC Timing Pipeline Delay When VCO Divider Is Used

INPUT TO CLK

INPUT TO CHANNEL DIVIDER

OUTPUT OF

CHANNEL DIVIDER

SYNC PIN

14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT

910

CHANNEL DIVIDER OUTPUT STATIC

CHANNEL DIVIDER

OUTPUT CLOCKING

CHANNEL DIVIDER

OUTPUT CLOCKING

Figure 40. SYNC Timing Pipeline Delay When VCO Divider Is Not Used

LVPECL Output Drivers

The LVPECL differential voltage (VOD) is selectable (from

~400 mV to 960 mV, see Bit 1 and Bit 2 in Register 0x0F0 to

power supply (VS_DRV), allowing a separate power supply to

be used. VS_DRV can be from 2.5 V or from 3.3 V.

The LVPECL output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring a

board layout change. Each LVPECL output can be powered

down or powered up as needed. Because of the architecture of

the LVPECL output stages, there is the possibility of electrical

overstress and breakdown under certain power-down conditions.

For this reason, the LVPECL outputs have two power-down

modes: total power-down and safe power-down.

In total power-down mode, all output drivers are shut off

simultaneously. This mode must not be used if there is an

external voltage bias network (such as Thevenin equivalent

termination) on the output pins that will cause a dc voltage to

appear at the powered down outputs. However, total power-

down mode is allowed when the LVPECL drivers are terminated

using only pull-down resistors. The total power-down mode is

activated by setting 0x230[1].

The primary power-down mode is the safe power-down mode.

This mode continues to protect the output devices while

powered down. There are three ways to activate safe power-

down mode: individually set the power-down bit for each

driver, power down an individual output channel (all of the

drivers associated with that channel are powered down

automatically), and activate sleep mode.

AD9520-5/PCBZ 数据表(PDF) 43 Page - Analog Devices

AD9520-5/PCBZ 数据表(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载

链接网址

AD9520-5/PCBZ 数据表(PDF) 43 Page - Analog Devices

AD9520-5/PCBZ 数据表(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表 下载

链接网址

数据表下载