AD9520-5SLASHPCBZ datasheet(73/80 Pages) AD

73 / 80 page

AD9520-5

Rev. 0 | Page 73 of 80

Table 51. VCO Divider and CLK Input

Reg.

Addr

(Hex) Bit(s) Name

Description

1E0

[2:0]

VCO divider

[2]

[1]

[0]

Divide

2 (default)

Output static

1 (bypass)

Output static

1E1

[4]

Power-down clock input section

Powers down the clock input section (including the CLK buffer, VCO divider, and CLK tree).

[4] = 0; normal operation (default).

[4] = 1; power down.

1E1

[0]

Bypass VCO divider

Bypasses or uses the VCO divider.

[0] = 0; use the VCO divider (default).

[0] = 1; bypass the VCO divider.

Table 52. System

Reg.

Addr

(Hex) Bit(s) Name

Description

230

[3]

Disable power-on SYNC

Power-on SYNC mode. Used to disable the antiruntpulse circuitry.

[3] = 0; enable the antiruntpulse circuitry (default).

[3] = 1; disable the antiruntpulse circuitry.

230

[2]

Power-down SYNC

Powers down the SYNC function.

[2] = 0; normal operation of the SYNC function (default).

[2] = 1; power-down SYNC circuitry.

230

[1]

Power-down distribution reference

Powers down the reference for the distribution section.

[1] = 0; normal operation of the reference for the distribution section (default).

[1] = 1; powers down the reference for the distribution section.

230

[0]

Soft SYNC

The soft SYNC bit works in the same way as the SYNC pin, except that the polarity of

the bit is reversed; that is, a high level forces selected channels into a predetermined

static state, and a 1-to-0 transition triggers a SYNC.

[0] = 0; same as SYNC high.

[0] = 1; same as SYNC low.

Table 53. Update All Registers

Reg.

Addr

(Hex) Bit(s) Name

Description

232

[0]

IO_UPDATE

This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens

on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0.

[0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.

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