AD9520-5SLASHPCBZ datasheet(33/80 Pages) AD

33 / 80 page

AD9520-5

Rev. 0 | Page 33 of 80

R and N Divider Delays

Both the R and N dividers feature a programmable delay cell.

These delays can be enabled to allow adjustment of the phase

relationship between the PLL reference clock and the VCO or

CLK. Each delay is controlled by three bits. The total delay

range is about 1 ns. See 0x019 in Table 2 and Table 48.

Digital Lock Detect (DLD)

By selecting the proper output through the mux on each pin, the

DLD function is available at the LD, STATUS, and REFMON pins.

The digital lock detect circuit indicates a lock when the time

difference of the rising edges at the PFD inputs is less than a

specified value (the lock threshold). The loss of a lock is indicated

when the time difference exceeds a specified value (the unlock

threshold). Note that the unlock threshold is wider than the

lock threshold, which allows some phase error in excess of the

lock window to occur without chattering on the lock indicator.

The lock detect window timing depends on the value of the

CPRSET resistor, as well as three settings: the digital lock

detect window bit (0x018[4]), the antibacklash pulse width

bit (0x017[1:0], see Table 2), and the lock detect counter

(0x018[6:5]). The lock and unlock detection values in Table 2

are for the nominal value of CPRSET = 5.11 kΩ. Doubling the

CPRSET value to 10 kΩ doubles the values in Table 2.

A lock is not indicated until there is a programmable number of

consecutive PFD cycles with a time difference less than the lock

detect threshold. The lock detect circuit continues to indicate a

lock until a time difference greater than the unlock threshold

occurs on a single subsequent cycle. For the lock detect to work

properly, the period of the PFD frequency must be greater than

the unlock threshold. The number of consecutive PFD cycles

required for a lock is programmable (0x018[6:5]).

Note that it is possible in certain low (<500 Hz) loop bandwidth,

high phase margin cases that the DLD can chatter during acqui-

sition, which can cause the AD9520 to automatically enter and exit

holdover. To avoid this problem, it is recommended that the

user make provisions for a capacitor to ground on the LD pin so

that current source digital lock detect (CSDLD) mode can be used.

Table 25. How a 10 MHz Reference Input Can Be Locked to Any Integer Multiple of N

fREF (MHz)

fVCO (MHz)

Mode

Notes

P = 1, B = 1 (bypassed)

P = 2, B = 1 (bypassed)

P = 1, B = 3

P = 1, B = 4

P = 1, B = 5

P = 2, B = 3

P and P + 1 = 2 and 3, A = 0, B = 3

P and P + 1 = 2 and 3, A = 1, B = 3

P and P + 1 = 2 and 3, A = 2, B = 3

P and P + 1 = 2 and 3, A = 1, B = 4

100

P = 2, B = 5

100

P and P + 1 = 2 and 3, A = 0, B = 5

110

P and P + 1 = 2 and 3, A = 1, B = 5

120

P = 2, B = 6

120

P and P + 1 = 2 and 3, A = 0, B = 6

120

P and P + 1 = 4 and 5, A = 0, B = 3

130

P and P + 1 = 4 and 5, A = 1, B = 3

1 X = don’t care.

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