AD9520-5SLASHPCBZ datasheet(63/80 Pages) AD

63 / 80 page

AD9520-5

Rev. 0 | Page 63 of 80

Reg.

Addr

(Hex) Bit(s) Name

Description

016

[3]

B counter

bypass

B counter bypass. This is only valid when operating the prescaler in FD mode.

[3] = 0; normal (default).

[3] = 1; B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for

the N divider.

016

[2:0]

Prescaler P

Prescaler: DM = dual modulus and FD = fixed divide. The Prescaler P is part of the feedback divider.

[2]

[1]

[0]

Mode

Prescaler

Divide-by-1.

Divide-by-2.

Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.

Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.

Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.

Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.

Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0 (default).

Divide-by-3.

017

[7:2]

STATUS

pin control

Selects the signal that appears at the STATUS pin. 0x01D[7] must be 0 to reprogram the STATUS pin.

[7]

[6]

[5]

[4]

[3]

[2]

Level or

Dynamic

Signal

Signal at STATUS Pin

LVL

Ground, dc (default).

DYN

N divider output (after the delay).

DYN

R divider output (after the delay).

DYN

A divider output.

DYN

Prescaler output.

DYN

PFD up pulse.

DYN

PFD down pulse.

LVL

Ground (dc); for all other cases of 0XXXXX not specified.

The selections that follow are the same as for REFMON.

LVL

Ground (dc).

DYN

REF1 clock (differential reference when in differential mode).

DYN

REF2 clock (N/A in differential mode).

DYN

Selected reference to PLL (differential reference when in

differential mode).

DYN

Unselected reference to PLL (not available in differential

mode).

LVL

Status of selected reference (status of differential reference);

active high.

LVL

Status of unselected reference (not available in differential

mode); active high.

LVL

Status REF1 frequency (active high).

LVL

Status REF2 frequency (active high).

LVL

(Status REF1 frequency) AND (status REF2 frequency).

LVL

(DLD) AND (status of selected reference) AND (status of VCO).

LVL

Status of CLK frequency (active high).

LVL

Selected reference (low = REF1, high = REF2).

LVL

DLD; active high.

LVL

Holdover active (active high).

LVL

LD pin comparator output (active high).

LVL

VS (PLL power supply).

DYN

REF1 clock (differential reference when in differential mode).

DYN

REF2 clock (not available in differential mode).

DYN

Selected reference to PLL (differential reference when in

differential mode).

AD9520-5/PCBZ 数据表(PDF) 63 Page - Analog Devices

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