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AD9525/PCBZ 数据表(PDF) 30 Page - Analog Devices |
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AD9525/PCBZ 数据表(HTML) 30 Page - Analog Devices |
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30 / 48 page  AD9525 Data Sheet Rev. 0 | Page 30 of 48 CS SCLK SDIO tHIGH tLOW tCLK tS tDS tDH tC BIT N BIT N + 1 Figure 33. Serial Control Port Timing—Write Table 27. Serial Control Port Timing Parameter Description tDS Setup time between data and rising edge of SCLK tDH Hold time between data and rising edge of SCLK tCLK Period of the clock tS Setup time between the CS falling edge and SCLK rising edge (start of communication cycle) tC Setup time between SCLK rising edge and the CS rising edge (end of communication cycle) tHIGH Minimum period that SCLK should be in a logic high state tLOW Minimum period that SCLK should be in a logic low state tDV SCLK to valid SDIO and SDO (see Figure 31) |
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