AD9525SLASHPCBZ datasheet(23/48 Pages) AD

23 / 48 page

Data Sheet

AD9525

Rev. 0 | Page 23 of 48

CLOCK DISTRIBUTION

The AD9525 can be used only as a clock fan out buffer by

disabling the PLL circuit blocks except for the clock distribution

section. The clock distribution consists of eight LVPECL clock

output drivers that share a common M divider. See the M Divider

section for more information on the common M divider.

Duty Cycle and Duty-Cycle Correction

The duty cycle of the clock signal at the output of a driver is

a result of either or both of the following conditions:

•

The CLKIN, CLKIN input duty cycle. If the CLKIN, CLKIN

input is routed directly to the output, the duty cycle of the

output is the same as the CLKIN, CLKIN input.

•

The M divider value. An odd M divider value results in

a non-50% duty cycle.

Table 23.Typical Output Duty Cycle with M Divider ≠ 1

M Divider

Output Duty Cycle (%)

Even

Odd = 3

33.3

Odd = 5

LVPECL Output Drivers

The LVPECL differential voltage (VOD) is selectable (from

~400 mV to 960 mV (see Bit 2 and Bit 1 in Register 0x0F0 to

The LVPECL output polarity can be set as noninverting or

inverting, which allows for the adjustment of the relative

polarity of outputs within an application without requiring

a board layout change. Each LVPECL output can be powered

down or powered up, as needed. Because of the architecture of

the LVPECL output stages, there is the possibility of electrical

overstress and breakdown under certain power-down conditions.

For this reason, the LVPECL outputs have two power-down modes:

total power-down and safe power-down. The primary power-

down mode is the safe power-down mode. This mode continues

to protect the output devices while powered down. There are three

ways to activate safe power-down mode: individually set the

power-down bit for each driver, power down an individual

output channel, or activate sleep mode.

In total power-down mode 0x0230[1] = 1 (power down

distribution reference). This mode must not be used if there is

an external voltage bias network (such as Thevenin equivalent

termination) on the output pins that will cause a dc voltage to

appear at the powered down outputs. However, total power-down

mode is allowed when the LVPECL drivers are terminated using

only pull-down resistors.

200Ω

SW1B

SW1A

SW2

QN2

QN1

OUT

4.4mA

Figure 22. LVPECL Output Simplified Equivalent Circuit

SYNC_OUT

SYNC_OUT provides one LVPECL output or two CMOS

output signal that can used to reset or synchronize a converter.

SYNC_OUT functionality block diagram is shown in Figure 23.

The SYNC_OUT signal is derived from the PLL phase detector

reference input clock or feedback (N-divider) clock. A program-

mable 16-bit S divider further divides the selected reference clock.

There are three different modes of operation for SYNC_OUT:

single shot, periodic, or pseudorandom. SYNC_OUT is retimed to

the high speed clock.

÷M

D SET

CLR

÷S

DIGITAL SYNC CONTROL

M DIVIDER OUTPUT

÷N

OUT0 TO OUT7

SYNC_OUT

PFD

SELECT REF: REF, FB, PD

DIGITAL LOCK DETECT

SYNC ENABLE

LOW

REF

Figure 23. SYNC_OUT Functional Diagram

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