AD9525SLASHPCBZ datasheet(1/48 Pages) AD

部件名	AD9525/PCBZ

功能描述	Low Jitter Clock Generator with Eight LVPECL Outputs

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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1 / 48 page

Low Jitter Clock Generator

with Eight LVPECL Outputs

Data Sheet

AD9525

Rev. 0

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FEATURES

Integrated ultralow noise synthesizer

8 differential 3.6 GHz LVPECL outputs and 1 LVPECL SYNC

output or 2 CMOS SYNC outputs

2 differential reference inputs and 1 single-ended reference

input

APPLICATIONS

LTE and multicarrier GSM base stations

Clocking high speed ADCs, DACs

ATE and high performance instrumentation

40/100 Gb/sec OTN line side clocking

Cable/DOCSIS CMTS clocking

Test and measurement

FUNCTIONAL BLOCK DIAGRAM

REFB

PLL

DIVIDERS

÷S

SPI CONTROL

AD9525

REFA

REFB

SYNC_OUT

REFC

CLKIN

OUT7

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

OUT0

Figure 1.

GENERAL DESCRIPTION

The AD9525 is designed to support converter clock requirements

for long-term evolution (LTE) and multicarrier GSM base station

designs.

The AD9525 provides a low power, multioutput, clock distribution

function with low jitter performance, along with an on-chip PLL

that can be used with an external VCO or VCXO. The VCO input

and eight LVPECL outputs can operate up to a frequency of

3.6 GHz. All outputs share a common divider that can provide

a division of 1 to 6.

The AD9525 offers a dedicated output that can be used to provide

a programmable signal for resetting or synchronizing a data

converter. The output signal is activated by a SPI write.

The AD9525 is available in a 48-lead LFCSP and can be operated

from a single 3.3 V supply. The external VCXO or VCO can

have an operating voltage of up to 5.5 V.

The AD9525 operates over the extended industrial temperature

range of −40°C to +85°C.

类似零件编号 - AD9525/PCBZ

制造商	部件名	数据表	功能描述
Analog Devices	AD9525	852Kb / 48P	Low Jitter Clock Generator with Eight LVPECL Outputs REV. A

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Analog Devices	AD9525	852Kb / 48P	Low Jitter Clock Generator with Eight LVPECL Outputs REV. A