AD9525SLASHPCBZ datasheet(43/48 Pages) AD

43 / 48 page

Data Sheet

AD9525

Rev. 0 | Page 43 of 48

Table 47. SYNC_OUT Control

Reg.

Addr.

(Hex)

Bits

Bit Name

Description

0x0F8

[7:5]

Don’t care

Don’t care.

SYNC_OUT

channel

power-down

Powers down SYNC_OUT channel.

0: enabled.

1: power-down (default).

Sync polarity

Polarity LVPECL mode.

0: noninverting (default).

1: inverting.

[2:1]

SYNC_OUT

level

Bit 1

Bit 0

VOD (mV)

400 (default)

600

780

960

SYNC_OUT

driver

power-down

0: enabled (default).

1: powers down LVPECL SYNC_OUT driver.

0x0F9

[7:5]

Don’t care

Don’t care.

Polarity CMOS

mode

Polarity CMOS mode. This bit is also used in conjunction with Register 0x0F8[3] when the driver is in CMOS

mode (Register 0x0F9[1] = 1).

Reg. 0x0F9[4]

Reg. 0x0F8[3]

SYNC OUT/SYNC OUTB

Noninverting/noninverting

Inverting/inverting

Noninverting/inverting

Inverting/noninverting

[3:2]

Enable CMOS

drivers

Sets the CMOS driver output configuration when Register 0x0F9[1] = 1.

Bit 3

Bit 2

SYNC_OUT

Tristate

CMOS mode

Use CMOS mode instead of LVPECL mode for SYNC_OUT.

0: LVPECL mode (default).

1: CMOS mode.

Sync out

resampling

edge select

SYNC_OUT resample edge select. Selects the M divider output edge used to resample the sync clock.

0: use rising edge of M clock (default).

1: use falling edge of M clock.

0x190

[7:0]

Sync clock

S divider

16-bit sync S divider, Bits[7:0] (LSB).

Cycles of reference clock = S Divider Bits[15:0] + 1. For example, [15:0] = 0 is 1 reference clock cycles,

[15:0] = 1 is 2 reference clock cycles … [15:0] = 65535 is 65536 reference clock cycles.

0x191

[7:0]

Sync clock

S divider

16-bit sync S divider, Bits[15:8] (MSB).

0x192

[7:5]

Don’t care

Don’t care.

Sync enable

0: disable SYNC_OUT (default).

1: Enable SYNC_OUT.

Note: Self-clearing for single shot sync.

[3:2]

Sync source

Bit 1

Bit 0

Select Reference for SYNC Clock

REF: reference input (default)

FB: PLL feedback N divider

Power-down: power down SYNC

[1:0]

Sync mode

Bit 1

Bit 0

Sync Mode

Single shot (default)

Periodic

Pseudorandom

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AD9525/PCBZ 数据表(PDF) 43 Page - Analog Devices

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