AD9525SLASHPCBZ datasheet(46/48 Pages) AD

46 / 48 page

AD9525

Data Sheet

Rev. 0 | Page 46 of 48

LVPECL CLOCK DISTRIBUTION

The LVPECL outputs (because they are open emitter) require

a dc termination to bias the output transistors. The simplified

equivalent circuit in Figure 22 shows the LVPECL output stage.

In most applications, a LVPECL far-end Thevenin termination

(see Figure 35) or Y-termination (see Figure 36) is

recommended. In both cases, VS of the receiving buffer should

match VS_DRV (VS_DRV = VDD3). If it does not match, ac

coupling is recommended (see Figure 37).

VS_DRV

LVPECL

50Ω

SINGLE-ENDED

(NOT COUPLED)

VS_DRV

LVPECL

127Ω

83Ω

Figure 35. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination

VS_DRV

LVPECL

Z0 = 50Ω

VS = VS_DRV

LVPECL

50Ω

Z0 = 50Ω

Figure 36. DC-Coupled 3.3 V LVPECL Y-Termination

VS_DRV

LVPECL

100Ω DIFFERENTIAL

(COUPLED)

TRANSMISSION LINE

LVPECL

100Ω

0.1nF

200Ω

Figure 37. AC-Coupled LVPECL with Parallel Transmission Line

LVPECL Y-termination is an elegant termination scheme that

uses the fewest components and offers both odd- and even-mode

impedance matching. Even-mode impedance matching is an

important consideration for closely coupled transmission lines

at high frequencies. Its main drawback is that it offers limited

flexibility for varying the drive strength of the emitter-follower

LVPECL driver. This can be an important consideration when

driving long trace lengths but is usually not an issue.

Thevenin-equivalent termination uses a resistor network to

provide 50 Ω termination to a dc voltage that is below VOL of

the LVPECL driver. In this case, VS_DRV on the AD9525

should equal VS of the receiving buffer. Although the resistor

combination shown results in a dc bias point of VS_DRV − 2 V,

the actual common-mode voltage is VS_DRV − 1.3 V because

there is additional current flowing from the AD9525 LVPECL

driver through the pull-down resistor.

SYNC_OUT DISTRIBUTION

The SYNC_OUT driver of the AD9525 can be configured as

CMOS drivers. When selected for use as CMOS drivers, each

output becomes a pair of CMOS outputs, each of which can be

individually turned on or off and set as inverting or noninverting.

Be sure to note the skew difference of using CMOS mode vs.

LVPECL mode.

When single-ended CMOS clocking is used, refer to the guidelines

presented in the following paragraphs.

Point-to-point connections should be designed such that each

driver has only one receiver, if possible. Connecting outputs in

this manner allows for simple termination schemes and minimizes

ringing due to possible mismatched impedances on the output

trace. Series termination at the source is generally required to

provide transmission line matching and/or to reduce current

transients at the driver.

The value of the resistor is dependent on the board design and

timing requirements (typically 10 Ω to 100 Ω is used). CMOS

outputs are also limited in terms of the capacitive load or trace

length that they can drive. Typically, trace lengths less than 3 inches

are recommended to preserve signal rise/fall times and signal

integrity.

CMOS

10Ω

60.4Ω

(1.0 INCH)

MICROSTRIP

Figure 38. Series Termination of CMOS Output

Termination at the far end of the PCB trace is a second option.

The SYNC_OUT CMOS output of the AD9525 does not supply

enough current to provide a full voltage swing with a low

impedance resistive, far-end termination, as shown in Figure 39.

The far-end termination network should match the PCB trace

impedance and provide the desired switching point. The reduced

signal swing may still meet receiver input requirements in some

applications. This can be useful when driving long trace lengths

on less critical nets.

CMOS

10Ω

50Ω

100Ω

Figure 39. CMOS Output with Far-End Termination

Because of the limitations of single-ended CMOS clocking,

consider using differential outputs when driving high speed

signals over long traces. The AD9525 offers SYNC_OUT

LVPECL outputs that are better suited for driving long traces

where the inherent noise immunity of differential signaling

provides superior performance for clocking converters.

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