AD9525SLASHPCBZ datasheet(37/48 Pages) AD

37 / 48 page

Data Sheet

AD9525

Rev. 0 | Page 37 of 48

Table 33. REF_MON Pin Control

Reg.

Addr.

(Hex)

Bits

Bit

Name

Description

0x018

[7:5]

Don’t

care

Don’t care.

[4:0]

REF_MON

control

Selects the signal that is connected to the REF_MON pin.

Bit 4

Bit 3

Bit2

Bit 1

Bit 0

Level or

Dynamic

Signal

Signal at REF_MON Pin

LVL

Ground (dc).

DYN

REFA clock.

DYN

REFB clock.

DYN

Selected reference clock to PLL.

DYN

Unselected reference clock to PLL.

LVL

Both reference clocks missing (active high).

LVL

Ground (dc).

LVL

Status REF A frequency (active high).

LVL

Status REF B frequency (active high).

LVL

(Status REF A frequency) AND (status REF B frequency).

LVL

(DLD) AND (status of selected reference) AND (status of feedback

clock).

LVL

Status of feedback clock (active high).

LVL

Selected reference (low: REFA, high: REFB).

LVL

DLD; active high.

LVL

N/A.

LVL

Ground, dc.

LVL

VDD3 (PLL power supply).

DYN

REFA.

DYN

REFB.

DYN

Selected reference to PLL.

DYN

Unselected reference to PLL.

LVL

Status of selected reference (status of differential reference); active low.

LVL

Status of unselected reference (not available in differential mode);

active low.

LVL

Status of REF A frequency (active low).

LVL

Status of REF B frequency (active low).

LVL

(Status of REFA frequency) AND (status of REFB frequency).

LVL

(DLD) AND (status of selected reference) AND (status of feedback clock).

LVL

Status of feedback clock (active low).

LVL

Selected reference (low: REFA, high: REFB); active low.

LVL

DLD (active low).

LVL

N/A.

LVL

VDD3 (PLL power supply).

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