AD9525SLASHPCBZ datasheet(24/48 Pages) AD

24 / 48 page

AD9525

Data Sheet

Rev. 0 | Page 24 of 48

Single Shot Mode

In single shot mode one sync pulse occurs after writing SYNC

ENABLE 0x192[4] = 1. An IO_UPDATE is required to complete

a register write. The width of the sync pulse is determined by the

value of the S divider. A divider value of 0x0000 allows a pulse

whose width is equal to one half period of the phase detector rate.

A divider value of 0x0001 allows a pulse whose width is equal

to two half periods of the phase detector rate. In single shot

mode, the sync enable bit is self-clearing and the sync circuits

are ready to receive another sync enable.

Periodic Mode

In periodic mode, the pulse is continuous until SYNC ENABLE

is cleared by a register writing SYNC ENABLE 0x192[4] = 0.

An IO_UPDATE is required to complete a register write. The

width of the sync pulse is equal to one half period of the phase

detector rate. The pulse repetition rate is determined by the

value of the S divider. A divider value of 0x0000 allows a pulse

rate equal to the phase detector rate. A divider value of 0x0001

allows a pulse rate equal to two half periods of the phase detector

rate. The SYNC_OUT signal is resampled with the OUT clock

to ensure time alignment and minimum output skew. There is a

possibility in periodic mode that the SYNC_OUT could slip one

half cycle of the OUT clock period.

Pseudorandom Mode

Pseudorandom mode is similar to periodic mode but the pulse

is a PN17 sequence that is continuous until SYNC ENABLE is

cleared by a register writing SYNC ENABLE 0x192[4] = 0. An

IO_UPDATE is required to complete a register write. The width

of the sync pulse is equal to one half period the phase detector

rate. The pulse repetition rate is determined by the value of the

S divider. A divider value of 0x0000 allows a pulse rate equal to

the phase detector rate. A divider value of 0x0001 allows pulse

rate equal to two half the phase detector rate.

SYNC_OUT Programming

The procedure to configure the SYNC_OUT depends on the

logic requirement of the converters that require synchroniza-

tion. Analog Devices, Inc., converters are synchronized on the

rise edge of the SYNC pulse.

SYNC_OUT CMOS Driver

The user can also configure the LVPECL SYNC_OUT as a pair

of CMOS outputs. When the output is configured as CMOS,

CMOS Output A and CMOS Output B are automatically turned

on. Either CMOS Output A or Output B can be turned on or off

independently. The user can also select the relative polarity of the

CMOS outputs for any combination of inverting and noninverting

(see Register 0x0F9). The user can power down each CMOS output

as needed to save power. The CMOS driver is in tristate when it is

powered down.

REF CLOCK

SYNC_OUT

MODE = SINGLE SHOT

S DIVIDER = 0

SYNC_OUT

MODE = PERIODIC

SYNC ENABLE = LOW

(SINGLE SHOT SELF CLEARING)

IO_UPDATE

SYNC_OUT

MODE = PN17

tSTOP

tSTART

SYNC ENABLE = HIGH

(SINGLE SHOT SELF CLEARING)

IO_UPDATE

Figure 24. SYNC Output Timing

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