AD9525SLASHPCBZ datasheet(25/48 Pages) AD

25 / 48 page

Data Sheet

AD9525

Rev. 0 | Page 25 of 48

PROGRAM: S DIVIDER,

SYNC MODE

PROGRAM: SYNC

ENABLE

SYNC_OUT

CONTROL

SYNC ENABLE

LOW?

END SYNC

PROCESS

LOCK

DETECT = HIGH

DIGITAL LOCK DETECT

IS USED TO PREVENT

OCCURENCE OF SYNC

IF PLL IS UNLOCKED

ENABLE_ANALOG

YES

SYNC LOW

YES

SYNC HIGH FOR S DIVIDER + 1

REF CLOCK CYCLES

THE ANALOG CLOCK

TO THE DIGITAL STATE

MACHINE IS

DISABLED IF SYNC

IS DISABLED

USER PROGRAMS

FOR S DIVIDER

AND SYNC MODE

REQUEST SYNC

PROGRAM: IO UPDATE

SYNC ENABLE IS SELF

CLEARING IN SINGLE

SHOT MODE. OTHER

MODES REQUIRE A

SPI WRITE TO DISABLE

SYNC_OUT

Figure 25. SYNC_OUT Flowchart

RESET MODES

The AD9525 has a power-on reset (POR) and several other

ways to apply a reset condition to the chip.

Power-On Reset

During chip power-up, a power-on reset pulse is issued when

VDD reaches ~2.6 V (<2.8 V) and restores the chip to the

default on-chip setting. It takes ~70 ms for the outputs to begin

toggling after the power-on reset pulse signal is internally

generated. The default power-on state of the AD9525 is

configured as a buffer.

Hardware Reset via the RESET Pin

RESET, a hard reset (an asynchronous hard reset is executed by

briefly pulling RESET low), restores the chip to the on-chip

default register settings. It takes ~2 µs for the outputs to begin

toggling after RESET is issued.

Soft Reset via the Serial Port

The serial port control register allows for a soft reset by setting

Bit 2 and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set,

the chip enters a soft reset mode and restores the chip to the on-

chip setting, except for Register 0x000. Except for the self-clearing

bits, Bit 2 and Bit 5, Register 0x000 retains its previous value

prior to reset. These bits are self-clearing. However, the self-clearing

operation does not complete until an additional serial port SCLK

cycle occurs, and the AD9525 is held in reset until that happens.

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