AD9525SLASHPCBZ datasheet(34/48 Pages) AD

34 / 48 page

AD9525

Data Sheet

Rev. 0 | Page 34 of 48

Table 31. REFA, REFB, REFC, B, N, and P Dividers

Reg.

Addr.

(Hex)

Bits

Bit Name

Description

0x011

[7:4]

REFB divider output

high cycles

Divider high cycle word. Normally set to one-half desired divider division minus one:

for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).

Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A

value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

[3:0]

REFB divider output

low cycles

Divider low cycle word. Normally set to one-half desired divider division minus one:

for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).

Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A

value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

0x012

[7:4]

REFA divider output

high cycles

Divider high cycle word. Normally set to one-half desired divider division minus one:

for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).

Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A

value of 0x7 means the divider is high for eight input clock cycles (default: 0x0).

[3:0]

REFA divider output

low cycles

Divider low cycle word. Normally set to one-half desired divider division minus one:

for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).

Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A

value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

0x013

[7:4]

B divider output

high cycles

Divider high cycle word. Normally set to one-half desired divider division minus one:

for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).

Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A

value of 0x7 means the divider is high for eight input clock cycles (default: 0x0).

[3:0]

B divider output

low cycles

Divider low cycle word. Normally set to one-half desired divider division minus one:

for example, D/2 – 1; therefore, for Divide = 8, set to 0x03 (8/2 – 1).

Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A

value of 0x7 means that the divider is low for eight input clock cycles (default: 0x0).

0x014

[7:6]

Don’t care

Don’t care.

B divider bypass

Bypasses and powers down the B divider; routes input to divider output.

0: uses divider (default).

1: B divider is set to divide-by-1.

REFB divider bypass

Bypasses and powers down the divider; routes input to divider output.

0: uses divider (default).

1: REFB divider is set to divide-by-1.

REFA divider bypass

Bypasses and powers down the divider; routes input to divider output.

0: use divider (default).

1: REFA divider is set to divide-by-1.

[2:0]

P divider prescaler

P divider value (B divider prescaler).

Bit 2

Bit 1

Bit 0

Divider Value

1(default)

Static

0x015

Don’t care

Don’t care.

Reserved

0 (default).

Reserved

0 (default).

Reserved

0 (default).

B divider reset

Resets B divider.

0: normal operation (default).

1: holds B divider in reset.

AD9525/PCBZ 数据表(PDF) 34 Page - Analog Devices

AD9525/PCBZ 数据表(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表下载

链接网址

AD9525/PCBZ 数据表(PDF) 34 Page - Analog Devices

AD9525/PCBZ 数据表(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

数据表 下载

链接网址

数据表下载