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AD9525/PCBZ 数据表(PDF) 10 Page - Analog Devices

部件名 AD9525/PCBZ
功能描述  Low Jitter Clock Generator with Eight LVPECL Outputs
PDF  48 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9525/PCBZ 数据表(HTML) 10 Page - Analog Devices

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AD9525
Data Sheet
Rev. 0 | Page 10 of 48
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CLK = 1474.56 MHz, FOUT = 1474.56 MHz
Divider = 1
At 10 Hz Offset
−114
dBc/Hz
At 100 Hz Offset
−125
dBc/Hz
At 1 kHz Offset
−134
dBc/Hz
At 10 kHz Offset
−144
dBc/Hz
At 100 kHz Offset
−149
dBc/Hz
At 800 kHz Offset
−151
dBc/Hz
At 1 MHz Offset
−151
dBc/Hz
At 10 MHz Offset
−154
dBc/Hz
CLK = 122.88 MHz, FOUT = 122.88 MHz
Divider = 1
At 10 Hz Offset
−134
dBc/Hz
At 100 Hz Offset
−145
dBc/Hz
At 1 kHz Offset
−153
dBc/Hz
At 10 kHz Offset
−159
dBc/Hz
At 100 kHz Offset
−161
dBc/Hz
At 800 kHz Offset
−161
dBc/Hz
At 1 MHz Offset
−161
dBc/Hz
At 10 MHz Offset
−161
dBc/Hz
PD, RESET, AND REF_SEL PINS
Table 17.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT CHARACTERISTICS
Logic 1 Voltage
2.0
V
Logic 0 Voltage
0.8
V
Logic 1 Current
1
µA
Logic 0 Current PD, RESET
−112
µA
The minus sign indicates that current is flowing out of
the AD9525, which is due to the internal pull-up
resistor
Logic 0 Current REF_SEL
1
µA
Capacitance
2
pF
RESET TIMING
Pulse Width Low
50
ns
RESET Inactive to Start of Register
Programming
100
ns
STATUS AND REF_MON PINS
Table 18.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS
1 mA output load
Output Voltage High, VOH
2.7
V
Output Voltage Low, VOL
0.4
V
MAXIMUM TOGGLE RATE
200
MHz
Applies when mux is set to any divider or counter
output or PFD up/down pulse; usually debug mode
only; beware that spurs can couple to output when any
of these pins is toggling



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