AD9525SLASHPCBZ datasheet(7/48 Pages) AD

7 / 48 page

Data Sheet

AD9525

Rev. 0 | Page 7 of 48

TIMING CHARACTERISTICS

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

PROPAGATION DELAY, tPECL, CLKIN TO LVPECL OUTPUT

Termination as shown in Figure 35

For All M Divider Values

461

522

600

High frequency clock distribution configuration

Variation with Temperature

388

fs/°C

OUTPUT SKEW, LVPECL OUTPUTS1

All LVPECL Outputs

13.5

25.2

Across temperature and VDD per device

Temperature Coefficient

fs/°C

All LVPECL Outputs Across Multiple Parts

144

OUTPUT SKEW, LVPECL-TO-SYNC_OUT1

SYNC_OUT LVPECL Mode

All LVPECL Outputs

189

298

Across temperature and VDD per device

Temperature Coefficient

543

fs/°C

All LVPECL Outputs Across Multiple Parts

417

SYNC_OUT CMOS Mode

All LVPECL Outputs

1.64

2.34

Across temperature and VDD per device

All LVPECL Outputs Across Multiple Parts

2.46

PROPAGATION DELAY, REF TO LVPECL OUTPUT

267

581

924

REF refers to either REFA/REFA or REFB/REFB pairs

The output skew is the difference between any two paths while operating at the same voltage and temperature.

Timing Diagrams

CLK

tCMOS

tCLK

tPECL

Figure 2. CLK/CLK to Clock Output Timing, M Divider = 1

DIFFERENTIAL

LVPECL

80%

20%

tRP

tFP

Figure 3. LVPECL Timing, Differential

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