AD9525SLASHPCBZ datasheet(45/48 Pages) AD

45 / 48 page

Data Sheet

AD9525

Rev. 0 | Page 45 of 48

APPLICATIONS INFORMATION

FREQUENCY PLANNING USING THE AD9525

The AD9525 is a highly flexible PLL. When choosing the PLL

settings and version of the AD9525, the following guidelines

should be kept in mind.

The AD9525 has three frequency dividers: the reference (or R)

divider, the feedback (or N) divider, and the M divider. When

trying to achieve a particularly difficult frequency divide ratio

requiring a large amount of frequency division, some of the

frequency division can be done by either the M divider or the

N divider, thus allowing a higher phase detector frequency and

more flexibility in choosing the loop bandwidth.

Choosing a nominal charge pump current in the middle of the

allowable range as a starting point allows the designer to increase or

decrease the charge pump current and, thus, allows the designer

to fine-tune the PLL loop bandwidth in either direction.

ADIsimCLK is a powerful PLL modeling tool that can be

downloaded from www.analog.com. It is very accurate in

determining the optimal loop filter for a given application.

USING THE AD9525 OUTPUTS FOR ADC CLOCK

APPLICATIONS

Any high speed ADC is extremely sensitive to the quality of the

sampling clock of the AD9525. An ADC can be thought of as a

sampling mixer, and any noise, distortion, or time jitter on the

clock is combined with the desired signal at the analog-to-digital

output. Clock integrity requirements scale with the analog input

frequency and resolution, with higher analog input frequency

applications at ≥14-bit resolution being the most stringent. The

theoretical SNR of an ADC is limited by the ADC resolution and

the jitter on the sampling clock. Considering an ideal ADC of

infinite resolution, where the step size and quantization error

can be ignored, the available SNR can be expressed, approxi-

mately, by













SNR

log

(dB)

where:

fA is the highest analog frequency being digitized.

tJ is the rms jitter on the sampling clock.

Figure 34 shows the required sampling clock jitter as a function

of the analog frequency and effective number of bits (ENOB).

fA (MHz)

100

110

J = 100f

J = 200f

J = 400f

J = 1p

J = 2p

J = 10p

SNR = 20log

2πfAtJ

Figure 34. SNR and ENOB vs. Analog Input Frequency

For more information, see the AN-756 Application Note,

Sampled Systems and the Effects of Clock Phase Noise and Jitter,

and the AN-501 Application Note, Aperture Uncertainty and

ADC System Performance, at www.analog.com.

Many high performance ADCs feature differential clock inputs

to simplify the task of providing the required low jitter clock on

a noisy PCB. Distributing a single-ended clock on a noisy PCB can

result in coupled noise on the sampling clock. Differential distri-

bution has inherent common-mode rejection that can provide

superior clock performance in a noisy environment. The

differential LVPECL outputs of the AD9525 enable clock

solutions that maximize converter SNR performance.

The input requirements of the ADC (differential or single-ended,

logic level termination) should be considered when selecting

the best clocking/converter solution.

AD9525/PCBZ 数据表(PDF) 45 Page - Analog Devices

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