AD9525SLASHPCBZ datasheet(36/48 Pages) AD

36 / 48 page

AD9525

Data Sheet

Rev. 0 | Page 36 of 48

Reg.

Addr.

(Hex)

Bits

Bit Name

Description

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Level or

Dynamic

Signal

Signal at STATUS Pin

LVL

(DLD) AND (selected reference present)

AND (feedback clock present).

LVL

Feedback clock present (active high).

LVL

Selected reference (low: REFA, high: REFB).

LVL

DLD; active high.

LVL

N/A.

LVL

Ground (dc).

LVL

VDD3 (PLL power supply).

DYN

REFA clock.

DYN

REFB clock.

DYN

Selected reference to PLL.

DYN

Unselected reference to PLL.

LVL

Status of selected reference (status of

differential reference); active low.

LVL

Both reference clocks missing; active low.

LVL

REFA present (active low).

LVL

REFB present (active low).

LVL

(REFA present) AND (REFB present).

LVL

(DLD) AND (selected reference present)

AND (feedback clock present); (active low).

LVL

Feedback clock present

LVL

Selected reference (low = REFA, high =

REFB); active low.

LVL

DLD (active low).

LVL

N/A.

LVL

VDD3 (PLL power supply).

AD9525/PCBZ 数据表(PDF) 36 Page - Analog Devices

AD9525/PCBZ 数据表(HTML) 36 Page - Analog Devices

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