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AD9525/PCBZ 数据表(PDF) 31 Page - Analog Devices |
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AD9525/PCBZ 数据表(HTML) 31 Page - Analog Devices |
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31 / 48 page  Data Sheet AD9525 Rev. 0 | Page 31 of 48 CONTROL REGISTERS CONTROL REGISTER MAP OVERVIEW Register addresses that are not listed in Table 28 are not used, and writing to those registers has no effect. Registers that are marked as reserved should never have their values changed. When writing to registers with bits that are marked reserved, the user should take care to always write the default value for the reserved bits. Table 28. Control Register Map Reg. Addr. (Hex) Register Name (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 Default Value (Hex) Serial Port Configuration 0x000 SPI mode serial port configuration SD0 active LSB first/ address increase Soft reset Don't care Don't care Soft reset LSB first/ address increase SD0 active 0x00 Don't care Don't care Soft reset Don't care Don't care Soft reset Don't care Don't care 0x00 0x004 Readback control Don't care Don't care Don't care Don't care Don't care Don't care Don't care Read back active regs 0x00 PLL Configuration 0x010 PFD charge pump PFD polarity CP current, Bits[2:0] CP mode, Bits[1:0] Antibacklash pulse width, Bits[1:0] 0x7D 0x011 R dividers REFB divider output high cycles, Bits[3:0] REFB divider output low cycles, Bits[3:0] 0x00 0x012 REFA divider output high cycles, Bits[3:0] REFA divider output low cycles, Bits[3:0] 0x00 0x013 B divider B divider output high cycles, Bits[3:0] B divider output low cycles, Bits[3:0] 0x00 0x014 N divider Don't care Don't care B divider bypass REFB divider bypass REFA divider bypass P divider prescaler, Bits[2:0] 0x00 0x015 Resets Don't care Reserved Reserved Reserved B divider reset REFB divider reset REFA divider reset Reset all dividers 0x00 0x016 REFC REFC enable REFC divider, Bits[6:0] 0x00 0x017 Status pin Charge pump pin to VDD_CP/2 STATUS pin divider enable STATUS output select, Bits[5:0] 0x00 0x018 REF_MON pin control Don’t care Don’t care Don’t care REF_MON pin control, Bits[4:0] 0x00 0x019 Lock detect Don't care Don't care Don't care Don’t care Lock detect counter, Bits[1:0] Digital lock detect window Digital lock det disable 0x00 0x01A Ref switchover and monitors Enable FB clock present monitor Enable REFB present monitor Enable REFA present monitor Disable switchover deglitch Select REFB (manual register mode) Stay on REFB Use REF_SEL pin for reference switchover Enable automatic reference switchover 0x00 0x01B Reserved Reserved = 0 Reserved = 0 Reserved = 0 Reserved = 0 Reserved = 0 Reserved = 0 Reserved = 0 0x00 0x01C PLL block PD register N divider ECL 2 CMOS PD N divider PD R Divider B ECL 2 CMOS PD R Divider A ECL 2 CMOS PD R Divider B PD R Divider A PD R Channel B PD R Channel A PD 0x22 0x01F PLL readback Unused Unused Unused Selected reference Status FB clock Status REFB Status REFA Digital lock detect (DLD) N/A PECL/CMOS Outputs 0x0F0 LVPECL OUT0 Don’t care Don’t care Don’t care Power down Channel 0, Channel 1 Don't care OUT0 PECL output level, Bits[1:0] Power down PECL driver 0x04 0x0F1 LVPECL OUT1 Don’t care Don’t care Don’t care Reserved Don't care OUT1 PECL output level, Bits[1:0] Power down PECL driver 0x04 0x0F2 LVPECL OUT2 Don’t care Don’t care Don’t care Power down Channel 2, Channel 3 Don't care OUT2 PECL output level, Bits[1:0] Power down PECL driver 0x04 0x0F3 LVPECL OUT3 Don’t care Don’t care Don’t care Reserved Don't care OUT3 PECL output level, Bits[1:0] Power down PECL driver 0x04 |
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