AD9525SLASHPCBZ datasheet(11/48 Pages) AD

11 / 48 page

Data Sheet

AD9525

Rev. 0 | Page 11 of 48

SERIAL CONTROL PORT

Table 19.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS (INPUT)

CS has an internal 30 kΩ pull-up resistor

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

2.5

µA

Input Logic 0 Current

−112

µA

The minus sign indicates that current is flowing out of the

AD9525, which is due to the internal pull-up resistor

Input Capacitance

SCLK (INPUT)

SCLK has an internal 30 kΩ pull-down resistor

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

112

µA

Input Logic 0 Current

µA

Input Capacitance

SDIO (WHEN INPUT)

Input Logic 1 Voltage

2.0

Input Logic 0 Voltage

0.8

Input Logic 1 Current

Input Logic 0 Current

Input Capacitance

SDIO, SDO (OUTPUTS)

1 mA load current

Output Logic 1 Voltage

2.7

Output Logic 0 Voltage

0.4

TIMING

Clock Rate (SCLK, 1/tSCLK)

MHz

Pulse Width High, tHIGH

Pulse Width Low, tLOW

SDIO to SCLK Setup, tDS

SCLK to SDIO Hold, tDH

1.1

SCLK to Valid SDIO and SDO, tDV

CS to SCLK Setup and Hold, tS, tH

CS Minimum Pulse Width High, tPWH

3.6

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