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JS28F256P33BFE 数据表(PDF) 53 Page - Micron Technology

部件名 JS28F256P33BFE
功能描述  NumonyxTM StrataFlash Embedded Memory
PDF  90 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

JS28F256P33BFE 数据表(HTML) 53 Page - Micron Technology

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Datasheet
Aug 2009
53
Order Number:320003-08
P33-65nm
.
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned. See
Section 11.1.3, “End of Word Line (EOWL) Considerations” on
page 37 for more information
Figure 20: Synchronous Single-Word Array or Non-array Read Timing
Figure 21: Continuous Burst Read, showing an Output Delay Timing
R312
R305
R304
R4
R17
R307
R15
R9
R7
R8
R303
R102
R3
R104
R106
R101
R104
R105
R105
R2
R306
R301
CLK [C]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
R305
R305
R305
R305
R304
R4
R7
R312
R307
R15
R303
R102
R3
R106
R105
R105
R101
R2
R304
R304
R304
R306
R302
R301
CLK [C]
Address [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]



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