JS28F256P33BFE datasheet(34/90 Pages) MICRON

34 / 90 page

P33-65nm

Datasheet

Aug 2009

Order Number: 320003-08

11.0.1

Clear Status Register

The Clear Status Register command clears the status register. It functions independent

of VPP. The WSM sets and clears SR[7,6,2], but it sets bits SR[5:3,1] without clearing

them. The Status Register should be cleared before starting a command sequence to

avoid any ambiguity. A device reset also clears the Status Register.

11.1

Read Configuration Register

The RCR is used to select the read mode (synchronous or asynchronous), and it defines

the synchronous burst characteristics of the device. To modify RCR settings, use the

Configure Read Configuration Register command (see Section 6.2, “Device Command

Bus Cycles” on page 18).

RCR contents can be examined using the Read Device Identifier command, and then

reading from offset 0x05 (see Section 7.3, “Read Device Identifier” on page 22).

The RCR is shown in Table 11. The following sections describe each RCR bit.

Table 11: Read Configuration Register Description (Sheet 1 of 2)

Read Configuration Register (RCR)

Read

Mode

Latency Count

WAIT

Polarity

RES

WAIT

Delay

Burst

Seq

CLK

Edge

RES

Burst

Wrap

Burst Length

LC[3:0]

BL[2:0]

Bit

Name

Description

Read Mode (RM)

0 = Synchronous burst-mode read

1 = Asynchronous page-mode read (default)

14:11

Latency Count (LC[3:0])

0010 =Code 2

0011 =Code 3

0100 =Code 4

0101 =Code 5

0110 =Code 6

0111 =Code 7

1000 =Code 8

1001 =Code 9

1010 =Code 10

1011 =Code 11

1100 =Code 12

1101 =Code 13

1110 =Code 14

1111 =Code 15 (default)

(Other bit settings are reserved)

WAIT Polarity (WP)

0 =WAIT signal is active low (default)

1 =WAIT signal is active high

Reserved (R)

Default “0”, Non-changeable

8WAIT Delay (WD)

0 =WAIT deasserted with valid data

1 =WAIT deasserted one data cycle before valid data (default)

Burst Sequence (BS)

Default “0”, Non-changeable

Clock Edge (CE)

0 = Falling edge

1 = Rising edge (default)

5:4

Reserved (R)

Default “0”, Non-changeable

JS28F256P33BFE 数据表(PDF) 34 Page - Micron Technology

JS28F256P33BFE 数据表(HTML) 34 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表下载

链接网址

JS28F256P33BFE 数据表(PDF) 34 Page - Micron Technology

JS28F256P33BFE 数据表(HTML) 34 Page - Micron Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90

数据表 下载

链接网址

数据表下载