JS28F256P33BFE datasheet(54/90 Pages) MICRON

54 / 90 page

P33-65nm

Datasheet

Aug 2009

Order Number: 320003-08

Note:

WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and

deasserted during valid data (RCR.10=0, WAIT asserted low).

15.4

AC Write Specifications

Figure 22: Synchronous Burst-Mode Four-Word Read Timing

Table 24: AC Write Specifications (Sheet 1 of 2)

Num

Symbol

Parameter

Min

Max

Unit

Notes

tPHWL

RST# high recovery to WE# low

150

1,2,3

tELWL

CE# setup to WE# low

1,2,3

tWLWH

WE# write pulse width low

1,2,4

tDVWH

Data setup to WE# high

1,2

tAVWH

Address setup to WE# high

tWHEH

CE# hold from WE# high

tWHDX

Data hold from WE# high

tWHAX

Address hold from WE# high

tWHWL

WE# pulse width high

1,2,5

W10

tVPWH

VPP setup to WE# high

200

1,2,3,7

W11

tQVVL

VPP hold from Status read

W12

tQVBL

WP# hold from Status read

1,2,3,7

W13

tBHWH

WP# setup to WE# high

200

W14

tWHGL

WE# high to OE# low

1,2,9

W16

tWHQV

WE# high to read valid

tAVQV + 35

1,2,3,6,10

Write to Asynchronous Read Specifications

W18

tWHAV

WE# high to Address valid

1,2,3,6,8

R307

R10

R304

R305

R304

R17

R15

R303

R106

R102

R105

R101

R306

R302

R301

CLK [C]

Address [A]

ADV# [V]

CE# [E]

OE# [G]

WAIT [T]

Data [D/Q]

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